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<DIV>After PrologEpilogCodeInserter I found that the instructions that
restore callee saved registers S0,S1,LR are in the wrong location ,the
instructions are:</DIV>
<DIV>%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]</DIV>
<DIV>%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]</DIV>
<DIV>%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]</DIV>
<DIV>(LR is the Return address register)</DIV>
<DIV>the whole code of print-machineinstrs are:</DIV>
<DIV># After PrologEpilogCodeInserter:</DIV>
<DIV># Machine code for function L_mpy_ls: Post SSA</DIV>
<DIV>BB#0: derived from LLVM BB %0</DIV>
<DIV> Live Ins: %LR %S1 %S0</DIV>
<DIV>%SP<def> = ADDI %SP, -48</DIV>
<DIV>PROLOG_LABEL <MCSym=_tmp0></DIV>
<DIV>ST %LR<kill>, %SP, 44; mem:ST4[FixedStack0]</DIV>
<DIV>ST %S1<kill>, %SP, 40; mem:ST4[FixedStack1]</DIV>
<DIV>ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2]</DIV>
<DIV>PROLOG_LABEL <MCSym=_tmp1></DIV>
<DIV>%S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8)</DIV>
<DIV>ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8)</DIV>
<DIV>JSUB <ga:@extract_l>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>%V1<def> = ADDI %ZERO, 1</DIV>
<DIV>ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-5](align=8)</DIV>
<DIV>ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-6]</DIV>
<DIV>JSUB <ga:@shr>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>%S1<def> = LD %SP, 52; mem:LD4[FixedStack-2]</DIV>
<DIV>%V1<def> = LIL 32767</DIV>
<DIV>%V0<def> = AND %V0<kill>, %V1<kill></DIV>
<DIV>ST %V0<kill>, %SP, 4; mem:ST4[FixedStack-8]</DIV>
<DIV>ST %S1, %SP, 0; mem:ST4[FixedStack-7](align=8)</DIV>
<DIV>JSUB <ga:@L_mult>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>%V1<def> = ADDI %ZERO, 15</DIV>
<DIV>ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-9](align=8)</DIV>
<DIV>ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-10]</DIV>
<DIV>JSUB <ga:@L_shr>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-11](align=8)</DIV>
<DIV>%S0<def> = COPY %V0</DIV>
<DIV>JSUB <ga:@extract_h>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-12](align=8)</DIV>
<DIV>ST %S1<kill>, %SP, 4; mem:ST4[FixedStack-13]</DIV>
<DIV>ST %V0<kill>, %SP, 8; mem:ST4[FixedStack-14](align=8)</DIV>
<DIV>%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]</DIV>
<DIV>%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]</DIV>
<DIV>%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]</DIV>
<DIV>JSUB <ga:@L_mac>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>%SP<def> = ADDI %SP, 48</DIV>
<DIV>RetLR %V0<imp-use></DIV></DIV>
<DIV> </DIV>
<DIV>what I want to get is :</DIV>
<DIV> ......</DIV>
<DIV>
<DIV>JSUB <ga:@extract_h>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-12](align=8)</DIV>
<DIV>ST %S1<kill>, %SP, 4; mem:ST4[FixedStack-13]</DIV>
<DIV>ST %V0<kill>, %SP, 8; mem:ST4[FixedStack-14](align=8)</DIV>
<DIV>JSUB <ga:@L_mac>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def></DIV>
<DIV>
<DIV>%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]</DIV>
<DIV>%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]</DIV>
<DIV>%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]</DIV></DIV>
<DIV>%SP<def> = ADDI %SP, 48</DIV>
<DIV>RetLR %V0<imp-use></DIV>
<DIV> </DIV>
<DIV>can you tell me the problem? Thank you!</DIV></DIV>
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<DIV><SPAN>
<DIV><SPAN style="FONT-SIZE: 10.5pt; FONT-FAMILY: ËÎÌå; COLOR: #000000">Best
Regards, <BR><BR>Jiangwei Xu</SPAN></DIV>
<DIV><SPAN style="FONT-SIZE: 10.5pt; FONT-FAMILY: ËÎÌå; COLOR: #000000">Shanghai
Jiao Tong University<BR>800 Dongchuan Road<BR>Shanghai, 200240<BR>P.R.China
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