<div dir="ltr">Hi all, <div>The problem is stack-coloring opt will impact MI scheduler, </div><div>so I give the -no-stack-coloring option to workaround it.<br></div><div><br></div><div>I don't know it's a potential bug or I miss something.</div>
<div>but i found this (<a href="http://marc.info/?l=llvm-commits&m=134635331431884&w=2">http://marc.info/?l=llvm-commits&m=134635331431884&w=2</a>)<br>this "old" mail said: "Merging stack slots before the MI scheduler could invalidate this form of alias analysis since two IR allocas can share a stack slot."</div>
<div><br></div><div><br></div><div>===========================</div><div>simple test program: <a href="http://goo.gl/zxmvOV">http://goo.gl/zxmvOV</a><br></div><div><br></div><div>MI scheduler with new<span style="color:rgb(0,0,0);white-space:pre-wrap"> model:</span><br>
</div><div><br></div><div>foo.new.noSC.s (<b>-no-stack-coloring</b> <b>-scheditins=false)</b> <br></div><div><div>.LBB2_4: </div><div> add r1, r8, r0 </div><div> add r2, r4, r0 </div>
<div> vldr d16, [r1] </div><div> add r0, r0, #128 </div><div> vldr d17, [r2] </div><div> cmp r0, r10 </div><div> vmla.f64 d17, d16, d10 <====</div><div> vldr d16, [r1, #8] </div>
<div> vstr d17, [r2] <====</div><div> vldr d17, [r2, #8] </div><div> vmla.f64 d17, d16, d10 </div><div> vldr d16, [r1, #16] </div><div> vstr d17, [r2, #8] </div><div> vldr d17, [r2, #16] </div>
<div> vmla.f64 d17, d16, d10 </div><div> vldr d16, [r1, #24] </div><div> vstr d17, [r2, #16] </div><div> vldr d17, [r2, #24] </div><div> vmla.f64 d17, d16, d10 </div></div><div>...</div><div><br>
</div><div>foo.new.s (-scheditins=false)<br></div><div> .LBB2_4: <br></div><div><div> add r1, r4, r0</div><div> add r2, r6, r0</div><div> vldr d16, [r1]</div><div> add r0, r0, #128</div><div> vldr d17, [r2]</div>
<div> cmp r0, r8</div><div> vmla.f64 d17, d16, d10 <====</div><div> vstr d17, [r2] <==== </div><div> vldr d16, [r1, #8]</div><div> vldr d17, [r2, #8]</div><div> vmla.f64 d17, d16, d10</div><div>
vstr d17, [r2, #8]</div><div> vldr d16, [r1, #16]</div><div> vldr d17, [r2, #16]</div><div> vmla.f64 d17, d16, d10</div><div> vstr d17, [r2, #16]</div><div> vldr d16, [r1, #24]</div><div> vldr d17, [r2, #24]</div>
<div> vmla.f64 d17, d16, d10</div></div><div><br></div><div>MI scheduler with <span style="color:rgb(0,0,0);white-space:pre-wrap">Itinerary model:</span></div><div><span style="color:rgb(0,0,0);white-space:pre-wrap"><br>
</span></div><div>foo.old.noSC.s <b>(-no-stack-coloring)</b></div><div><div>.LBB2_4:</div><div> add r1, r8, r0</div><div> vldr d22, [r1, #48] </div><div> vldr d23, [r1, #56]<==</div><div> vldr d24, [r1, #64]</div>
<div>....<br></div></div><div><div> vmul.f64 d22, d22, d9 </div><div> vmul.f64 d23, d23, d9<==</div><div> vmul.f64 d24, d24, d9</div><div>...</div></div><div><br></div><div>foo.old.s (always reuse d16)<br></div>
<div><div>.LBB2_4:</div><div> add r1, r4, r0</div><div> add r2, r6, r0</div><div> vldr d16, [r1] </div><div> add r0, r0, #128</div><div> cmp r0, r9</div><div> vmul.f64 d16, d16, d9 </div><div> vstr d16, [r2] </div>
<div> vldr d16, [r1, #8] <==</div><div> vmul.f64 d16, d16, d9 <==</div><div> vstr d16, [r2, #8] <==</div><div> vldr d16, [r1, #16]</div><div> vmul.f64 d16, d16, d9</div><div> vstr d16, [r2, #16]</div>
<div> vldr d16, [r1, #24]</div><div> vmul.f64 d16, d16, d9</div></div><div><br></div><div><br></div><div>By the way, has anyone use the new machine model to describe in-order pipeline machine?</div><div>Does new model support it now?</div>
<div><br></div><div><br></div><div>Thanks,</div><div>Kuan-Hsu<br></div><div><br></div><div class="gmail_extra"><br><br><div class="gmail_quote">2013/10/21 Zakk <span dir="ltr"><<a href="mailto:zakk0610@gmail.com" target="_blank">zakk0610@gmail.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="ltr">Hi Andy, I'm working on defining new machine model for my target,<br>
<div>But I don't understand how to define the in-order machine (reservation tables) in new model.</div><div><br></div><div>For example, if target has IF ID EX WB stages</div>
<div><br></div><div>should I do:<br></div><div><br></div><div>let BufferSize=0 in {</div><div><font color="#000000"><span style="white-space:pre-wrap">def IF: ProcResource<1>;
</span></font><span style="white-space:pre-wrap">def ID: ProcResource<1>;</span><font color="#000000"><span style="white-space:pre-wrap">
</span>
</font></div><div><span style="white-space:pre-wrap">def EX: ProcResource<1>;
</span><span style="white-space:pre-wrap">def WB: ProcResource<1>;</span><font color="#000000"><span style="white-space:pre-wrap"><br></span></font></div><div><span style="white-space:pre-wrap">}</span></div>
<div><span style="white-space:pre-wrap">def : WriteRes<WriteALU, [IF, ID, EX1, WB]> ;</span><br></div><div><font color="#000000"><span style="white-space:pre-wrap">
or </span></font></div><div><font color="#000000"><span style="white-space:pre-wrap"><br></span></font></div><div><font color="#000000"><span style="white-space:pre-wrap">define each stage as </span></font><span style="white-space:pre-wrap">SchedWrite type and use </span><span style="white-space:pre-wrap">WriteSequence to define this </span><span style="white-space:pre-wrap">sequence?</span></div>
<div><br></div><div><span style>Thanks,</span><br></div><div class="gmail_extra">Kuan-Hsu<div><div class="h5"><br><br><div class="gmail_quote">2013/10/16 Andrew Trick <span dir="ltr"><<a href="mailto:atrick@apple.com" target="_blank">atrick@apple.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word"><br><div><div>
<div>On Oct 15, 2013, at 9:28 PM, Zakk <<a href="mailto:zakk0610@gmail.com" target="_blank">zakk0610@gmail.com</a>> wrote:</div><br><blockquote type="cite"><div dir="ltr">Hi Andy, thanks for your help!!<div><div>The scheduled code by method A is same as B when using the new machine model. </div>
<div>it's make sense, but there is the another problem, the scheduled code is badly.</div>
<div><br></div><div>load/store instruction always reuse the same register</div></div></div></blockquote><div><br></div></div><div>I filed PR17593 with this information. However, I see opposite results from what you’re expecting. The code that uses fewer registers runs 4% faster on my cortex-a9. The integer unit is out-of-order.</div>
<div><br><blockquote type="cite"><div dir="ltr"><div><div>this is just because A9's <span style="white-space:pre-wrap">per-operand machine model is not </span><span style="white-space:pre-wrap">implemented </span>well? </div>
<div>By the way, why do you want to use the new machine model for mi-sched?<br></div></div></div></blockquote><div><br></div></div><div>I want to move all the targets we support to the new machine model so it will be easier to maintain the scheduler. Additionally, the new model is much more efficient and simpler (if you don’t use special features). It is also correct for both preRA and postRA. Note that in the case of A9, the .td file for the new machine model is horribly complicated because it handles load multiple instructions. The A9 itinerary doesn’t even attempt to do that. (This was done mainly to demonstrate the feature set of the new model, not because it’s terribly important). The new model for A9 is also complicated by a mapping from the old itinerary classes to the new machine model.</div>
<div><br></div><div>-Andy</div><div><div><br><blockquote type="cite"><div dir="ltr"><div><div>Thanks,</div><div><br></div><div>Kind regards<br></div><div>Kuan-Hsu</div><div><br></div></div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">2013/10/15 Andrew Trick <span dir="ltr"><<a href="mailto:atrick@apple.com" target="_blank">atrick@apple.com</a>></span><br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div style="word-wrap:break-word"><br><div><div><div>On Oct 14, 2013, at 3:27 AM, Zakk <<a href="mailto:zakk0610@gmail.com" target="_blank">zakk0610@gmail.com</a>> wrote:</div><br><blockquote type="cite">
<div dir="ltr">Hi all, <div>I meet this problem when <span style="font-family:arial,sans-serif;font-size:13.888888359069824px">compiling the</span> TREAM benchmark (<a href="http://www.cs.virginia.edu/stream/FTP/Code/" target="_blank">http://www.cs.virginia.edu/stream/FTP/Code/</a>) with enable-misched</div>
<div><br></div><div>The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code.</div></div></blockquote><div><br></div></div><div>A bug for this is welcome. Pretty soon, I’ll be verifying A9 performance and changing the default scheduler. When I do this, I’ll be using the new machine model:</div>
<div><br></div><div>(-mllvm) -sched-itins=false</div><div><br></div><div>However, some scheduler changes are required for that mode to fully enforce pipeline hazards.</div><div><br><blockquote type="cite"><div dir="ltr">
<div>so I rewrite a simple code as attached link (foo.c), and compiled with two different methods:<br>
</div><div><br></div><div><b><font face="arial, helvetica, sans-serif">method A:</font></b></div><div><b><font face="arial, helvetica, sans-serif">$clang -O3 foo.c -static -S -o foo.s -mllvm -enable-misched -mllvm -unroll-count=4 <font>--target=arm </font><font>-mfloat-abi=hard </font>-mcpu=cortex-a9 -fno-vectorize -fno-slp-vectorize</font></b></div>
<div><b><font face="arial, helvetica, sans-serif"><br></font></b></div><div><b><font face="arial, helvetica, sans-serif">and</font></b></div><div><b><font face="arial, helvetica, sans-serif"><br></font></b></div><div><b><font face="arial, helvetica, sans-serif">method B:</font></b></div>
<div><b><font face="arial, helvetica, sans-serif"><font>$clang foo.c -S -emit-llvm -o foo.bc --target=arm -mfloat-abi=hard -mcpu=cortex-a9</font><br></font></b></div><div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;direction:ltr;word-break:normal">
<font face="arial, helvetica, sans-serif"><b>$opt foo.bc -O3 -unroll-count=4 -o foo.opt.bc</b></font></div><b><font face="arial, helvetica, sans-serif">
</font></b><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;direction:ltr;word-break:normal"><font face="arial, helvetica, sans-serif"><b>$llc foo.opt.bc -o foo.opt.s -march=arm -mcpu=cortex-a9 -enable-misched</b></font><br>
</div></div></div></blockquote><div><br></div></div><div>You can try “clang -O3 -mllvm -disable-llvm-optzns …”. clang should generate the same bitcode, but skip the “opt” step.</div><div><br></div><div>If that doesn’t work it can be a nightmare trying to decompose the compilations steps with fidelity. You can try:</div>
<div>- clang -### … </div><div>- clang -mllvm -print-options …</div><div>- Passing a full triple to all tools with -mtriple</div><div>- Debug the TargetOptions fields</div><div>- -print-after-all to see which phase is different</div>
<div><br></div><div>Even if you get all the options right, the process of serializing and rereading the IR can affect the optimizations.</div><div><br></div><div>Sorry. I’ve been trying to think of a way to improve this situation.</div>
<div><br></div><div>-Andy</div><div><br></div><blockquote type="cite"><div><div dir="ltr"><div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;direction:ltr;word-break:normal">
</div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal">
<span style="font-size:12pt;font-family:Calibri">(ps. I had checked with debug-pass=structure, so I think they are </span><font face="Calibri"><span style="font-size:15.972221374511719px">equivalently)</span></font></div>
<div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><br></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><span style="font-family:Calibri;font-size:12pt">but the result is different: </span><br>
</div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><span style="font-size:12pt;font-family:Calibri">You can find the </span><font face="Calibri"><span style="font-size:15.972221374511719px">LBB1_4 of foo.s, it always reuses the same reg for computation, but LBB1_4 of foo.opt.s doesn't.</span></font></div>
<div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><font face="Calibri"><span style="font-size:15.972221374511719px"><br></span></font></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal">
<font face="Calibri"><span style="font-size:15.972221374511719px">My question is how to just use clang (method A) to achieve B result? <br>Or i am missing something here?</span></font></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal">
<font face="Calibri"><span style="font-size:15.972221374511719px"><br></span></font></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><span style="font-family:arial,sans-serif;font-size:13.888888359069824px">I really appreciate </span><span style="background-color:rgb(255,255,204);font-family:arial,sans-serif;font-size:13.888888359069824px">any</span><span style="font-family:arial,sans-serif;font-size:13.888888359069824px"> </span><span style="background-color:rgb(255,255,204);font-family:arial,sans-serif;font-size:13.888888359069824px">help and suggestions</span><span style="font-family:arial,sans-serif;font-size:13.888888359069824px">.</span><font face="Calibri"><span style="font-size:15.972221374511719px"><br>
</span></font></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal"><span style="font-family:arial,sans-serif;font-size:13.888888359069824px">Thanks</span><br></div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal">
<span style="font-family:arial,sans-serif;font-size:13.888888359069824px"><br></span></div>Kuan-Hsu<br><br>------- file link -------
</div><div><div style="margin-top:0pt;margin-bottom:0pt;margin-left:0in;word-break:normal">foo.c: <a href="http://goo.gl/nVa2K0" target="_blank">http://goo.gl/nVa2K0</a><br></div><div>foo.s: <a href="http://goo.gl/ML9eNj" target="_blank">http://goo.gl/ML9eNj</a></div>
<div>foo.opt.s: <a href="http://goo.gl/31PCnf" target="_blank">http://goo.gl/31PCnf</a></div></div></div></div>
_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu" target="_blank">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu/" target="_blank">http://llvm.cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></div></blockquote></div><br><br clear="all"><div><br></div>-- <br>
Best regards,<br>Kuan-Hsu<br><br><br>
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