<div dir="ltr"><div><div><div>Hi, Akira, <br><br></div>I found you maintain mips MipsSchedule.td. does it correct? in MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no ByPass info out there.<br>
</div>are you sure this reflects the real R4xxx/R5xxx processors. <br><br>why IILoad uses funcition unit ALU? <br>InstrItinData<IILoad , [InstrStage<3, [ALU]>]><br><br><br></div><div>for my previous question, I have new input after reading the code. pre-RA-sched is derived from ScheduleDAGSNodes, but post-RA-sched and mi-sched are both derived from ScheduleDAGInstrs.that means pre-RA-sched schedules SDNodes. post-RA-sched schedules MIs.<br>
<br>from -debug-pass=Structure, we can see that the order is "mi-sched"==> RegisterAllocation==>post-RA TD.<br><br> Simple Register Coalescing<br> Machine Instruction Scheduler<br> Machine Block Frequency Analysis<br>
...<br> Greedy Register Allocator<br> Virtual Register Rewriter<br>...<br> Post RA top-down list latency scheduler<br> Analyze Machine Code For Garbage Collection<br></div><div>...<br></div><div><br><br>
</div><div>for my testcase, I found -enable-misched is helpful for ARM, they reduce stall numbers from 205 to 160. however, mips is adverse impact. the stall number increases from 554 to 560. this doesn't make any sense. <br>
</div><div><br>thanks<br></div><div>--lx<br><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Sep 20, 2013 at 10:50 AM, Liu Xin <span dir="ltr"><<a href="mailto:navy.xliu@gmail.com" target="_blank">navy.xliu@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div><div><div>Akira, <br><br></div>Thanks you for response. <br><br>I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But I found mips codes are good enough by default. basically, I can not easily eyeball any bubbles. <br>
</div>I don't understand how they can do that without post-RA-sched. pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little information and they can only schedule node in topology order. It assumes any SU is one cycle delay. I don't think pre-ra-sched consider any pipeline details.<br>
<br></div>thanks,<br></div>--lx<br><div><div><div><div><br></div></div></div></div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Sep 20, 2013 at 5:39 AM, Akira Hatanaka <span dir="ltr"><<a href="mailto:ahatanak@gmail.com" target="_blank">ahatanak@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3.<br>
</div><div><br></div><div>You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options.</div>
<div><br></div><div>Currently, mips has only one generic scheduling itinerary model in MipsSchedule.td that is not tailored to any specific core, so you might have to tweak it to have the scheduler generate efficient code for your target.</div>
<div><br></div><div><br></div><div class="gmail_extra"><div class="gmail_quote"><div><div>On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <span dir="ltr"><<a href="mailto:navy.xliu@gmail.com" target="_blank">navy.xliu@gmail.com</a>></span> wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div><div dir="ltr"><div><div><div><div><div><div><div><div><div>Hi, LLVM, <br><br></div>I found LLVM codegen has 3 passes for instruction scheduling:<br>
<br></div>1) pre-ra sched<br></div>2) post-ra sched<br></div>3) mi sched. <br>
<br></div>for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW):<br></div><br>ld $t0, MEM<br></div>add $t2, $t0, $0<br><br></div>
There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict and insert other instructions to avoid pipeline bubble. I think this work only can be done after RA. If so, what's the purpose for 1). I found 1) is mandatory and 2/3) are optional. Further, at least one target enable pre-RA-sched with harzardRecognizer. Does it really work out? you can resolve data hazard using pre-RA-sched only? <br>
<br>thanks,<br></div><div>--lx<br><br></div><div><br></div><div><br><br><div><div><div><div><br><div><div><div><div><div><div><div><br></div></div></div></div></div></div></div></div></div></div></div></div></div>
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