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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">Hi Andrew,<br>
<br>
Thank you for the suggestion.<br>
I've looked at CodeGenPrepare.cpp and MoveExtToFormExtLoad() is never run.<br>
<br>
I also notice that the ARM target produces the same additional register usage (copy) and zero extending (of the copy).<br>
(See the usage of r3 &r5 and also r12 & r4 in attached file arm-strcspn.s, my understanding is that 'ldrb' is zero extending.)<br>
<br>
<br>
Here is a simplified example:<br>
void test(const char *c) {<br>
do {<br>
if (!*c) break;<br>
++c;<br>
} while (*c);<br>
}<br>
<br>
And in IR form:<br>
define void @test(i8* nocapture %c) {<br>
entry:<br>
%.pre = load i8* %c, align 1<br>
br label %do.body<br>
do.body:<br>
%0 = phi i8 [ %.pre, %entry ], [ %1, %if.end ]<br>
%c.addr.0 = phi i8* [ %c, %entry ], [ %incdec.ptr, %if.end ]<br>
%tobool = icmp eq i8 %0, 0<br>
br i1 %tobool, label %do.end, label %if.end<br>
if.end:<br>
%incdec.ptr = getelementptr inbounds i8* %c.addr.0, i64 1<br>
%1 = load i8* %incdec.ptr, align 1<br>
%tobool1 = icmp eq i8 %1, 0<br>
br i1 %tobool1, label %do.end, label %do.body<br>
do.end:<br>
ret void<br>
}<br>
<br>
<br>
The problem seems to be that an icmp becomes isolated in a different basic block to the originators of the vreg it uses viz:<br>
entry:<br>
%.pre = load i8* %c, align 1<br>
do.body:<br>
%0 = phi i8 [ %.pre, %entry ], [ %1, %if.end ]<br>
%tobool = icmp eq i8 %0, 0<br>
if.end:<br>
%1 = load i8* %incdec.ptr, align 1<br>
<br>
When a vreg is promoted during legalization, I assume there is knowledge that the top bits are zero.<br>
(assuming a ZEXTLOAD will be used - the only option for the xcore target)<br>
But when a vreg is subsequently truncated, can the top bits be known? viz:<br>
BB#1 'test:do.body'<br>
0x2c8d190: i32 = Register %vreg3<br>
0x2c8d590: i32,ch = CopyFromReg 0x2c5fcc0, 0x2c8d190 [ORD=4]<br>
0x2c8ce90: i8 = truncate 0x2c8d590 [ORD=4]<br>
0x2c8d990: i8 = Constant<0><br>
0x2c8d890: ch = seteq<br>
0x2c8d390: i1 = setcc 0x2c8ce90, 0x2c8d990, 0x2c8d890 [ORD=4]<br>
<br>
Is this what is happening?<br>
Can the Type-legalizer discover this information when lowering the truncate?<br>
Is the problem that this knowledge is not know in the DAG, only in the IR?<br>
<br>
Robert<br>
<br>
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