<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Sep 10, 2013, at 8:59 AM, Robert Lytton <<a href="mailto:robert@xmos.com">robert@xmos.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div ocsi="0" fpstyle="1" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="direction: ltr; font-family: Tahoma; font-size: 10pt;">Hi,<br><br>A bit more information.<br>I believe my problem lies with the fact that the load is left as 'anyext from i8'.<br>On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load!<br>If BB#1 were to force the load to a "zext from i8" would this information be available in BB#2?<br><br>BB#1:<br> 0x268c1b0: i32 = Register %vreg1 [ID=3]<br> 0x2689d80: i32,ch = load 0x265d380, 0x2689f80, 0x268b9b0<LD1[%s2], anyext from i8> [ORD=4] [ID=5]<br> 0x2689e80: ch = CopyToReg 0x265d380, 0x268c1b0, 0x2689d80 [ORD=4] [ID=6]<br><br>BB#2:<br> 0x268a480: i32 = Register %vreg1 [ID=1]<br> 0x268bbb0: i32,ch = CopyFromReg 0x265d380, 0x268a480 [ORD=6] [ID=7]<br> 0x268a080: i32 = Constant<255> [ID=6]<br> 0x268bdb0: i32 = and 0x268bbb0, 0x268a080 [ORD=6] [ID=8]<br> 0x2689e80: i32 = Constant<0> [ID=5]<br> 0x268c1b0: ch = seteq [ID=2]<br> 0x268a880: i32 = setcc 0x268bdb0, 0x2689e80, 0x268c1b0 [ORD=6] [ID=9]<br><br>Robert<br><br><div style="font-family: 'Times New Roman'; font-size: 16px;"><hr tabindex="-1"><div id="divRpF771975" style="direction: ltr;"><font face="Tahoma" size="2"><b>From:</b><span class="Apple-converted-space"> </span><a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [<a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>] on behalf of Robert Lytton [<a href="mailto:robert@xmos.com">robert@xmos.com</a>]<br><b>Sent:</b><span class="Apple-converted-space"> </span>06 September 2013 17:18<br><b>To:</b><span class="Apple-converted-space"> </span><a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br><b>Subject:</b><span class="Apple-converted-space"> </span>[LLVMdev] removing unnecessary ZEXT<br></font><br></div><div></div><div><div style="direction: ltr; font-family: Tahoma; font-size: 10pt;">Hi,<br><br>Within a basic block I can remove unnecessary register copies + zero sign extensions of unsigned-8bit-loaded values by implementing isZExtFree() for ISD::LOAD nodes.<br>...But not between basic blocks.<br><br>The first block does a CopyFromReg of the unsigned-8bit-loaded vreg1 into a new vreg2.<br>The second block then does a unnecessary zext to vreg2.<br>What I want is the 2nd block to use the original vreg1!<br>What I am getting is one extra register clobber and two extra instructions.<br><br>I have looked at other targets to see what they do but can't see what I am missing.<br><br>Help please!<br>Thank you<br><br>Robert<br></div></div></div></div></div></blockquote></div><div><br></div><div>The instruction selector only operates within a block. An IR CodeGenPrepare pass runs first and attempts to hoist the zext into the load’s block if it sees a legal zextload pattern (isLoadExtLegal). I’m not sure why the zero_extend isn’t hoisted in your case.</div><div>-Andy</div></body></html>