<div dir="ltr">I'm not very familiar with relocations but your fix looks the same as ARMTargetLowering::LowerCall, so from that perspective it lgtm (but I may be missing something).</div><div class="gmail_extra"><br><br>
<div class="gmail_quote">On Wed, Aug 21, 2013 at 8:04 AM, Logan Chien <span dir="ltr"><<a href="mailto:tzuhsiang.chien@gmail.com" target="_blank">tzuhsiang.chien@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr"><div>Hi Anton and JF,<br><br></div> Thanks for your review. After reading the source code more carefully, I have come up with a different way fix this issue. We can simply resolve this issue by adding ARMII::MO_PLT flags with MachineInstrBuilder in FastISel pass (without failing back to DAG lowering).<br>
<br> The new patch is attached, and the test case is not changed. Sorry for your inconvenience. Please have a look. Thanks for your help.<br><br>Sincerely,<br>Logan<br></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra">
<br><br><div class="gmail_quote">
On Wed, Aug 21, 2013 at 10:52 PM, JF Bastien <span dir="ltr"><<a href="mailto:jfb@google.com" target="_blank">jfb@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">lgtm</div><div><div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Aug 21, 2013 at 3:18 AM, Anton Korobeynikov <span dir="ltr"><<a href="mailto:anton@korobeynikov.info" target="_blank">anton@korobeynikov.info</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">LGTM<br>
<div><div><br>
On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <<a href="mailto:tzuhsiang.chien@gmail.com" target="_blank">tzuhsiang.chien@gmail.com</a>> wrote:<br>
> Hi,<br>
><br>
> I have created a workaround to deal with the PIC function call. With this<br>
> patch, the FastISel will switch back to DAG lowering mechanism if (1) there<br>
> is a function call in the basic block and (2) the relocation model is PIC.<br>
> Please have a look. Hoping the patch will help.<br>
><br>
> Sincerely,<br>
> Logan<br>
><br>
><br>
> On Wed, Aug 21, 2013 at 10:17 AM, Gordon Keiser <<a href="mailto:gkeiser@arxan.com" target="_blank">gkeiser@arxan.com</a>> wrote:<br>
>><br>
>> Cool, I'll file a bug tomorrow at work and add you to the CC list.<br>
>><br>
>> Thanks!<br>
>> Gordon Keiser<br>
>> Software Development Engineer<br>
>> Arxan Technologies<br>
>> <a href="mailto:gkeiser@arxan.com" target="_blank">gkeiser@arxan.com</a> <a href="http://www.arxan.com" target="_blank">www.arxan.com</a><br>
>> Protecting the App EconomyT<br>
>><br>
>> > -----Original Message-----<br>
>> > From: Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>]<br>
>> > Sent: Tuesday, August 20, 2013 9:47 PM<br>
>> > To: Gordon Keiser<br>
>> > Cc: <a href="mailto:llvmdev@cs.uiuc.edu" target="_blank">llvmdev@cs.uiuc.edu</a>; JF Bastien<br>
>> > Subject: Re: [LLVMdev] Broken PLT on ARM from R183966<br>
>> ><br>
>> > Filing a bug would be a good start, go ahead and cc me and<br>
>> > <a href="mailto:jfb@google.com" target="_blank">jfb@google.com</a>.<br>
>> ><br>
>> > Thanks!<br>
>> ><br>
>> > -eric<br>
>> ><br>
>> > On Tue, Aug 20, 2013 at 6:10 PM, Gordon Keiser <<a href="mailto:gkeiser@arxan.com" target="_blank">gkeiser@arxan.com</a>><br>
>> > wrote:<br>
>> > > For ARM targets on linux, revision 183966 made Fast ISel default.<br>
>> > > Unfortunately, Fast ISel is broken in terms of applying the<br>
>> > > ARMII::MO_PLT flags to calls in PIC mode (at least when emitting<br>
>> > > assembly); it never does this. The normal ISel pass handles this<br>
>> > > situation correctly so a temporary local change to disable FastISel<br>
>> > > for linux / NaCl targets is working for me right now.<br>
>> > ><br>
>> > ><br>
>> > ><br>
>> > > I'm not very familiar with the ISel passes. I'm guessing the correct<br>
>> > > thing to do here would be to apply the attribute correctly in FastISel<br>
>> > > so it works, but I'm kind of unfamiliar with this part of the code and<br>
>> > > won't have time to dig into it right now, although I'm willing to do<br>
>> > > it if someone points me to the right area of code.<br>
>> > ><br>
>> > ><br>
>> > ><br>
>> > > In the meantime, would it be worthwhile to submit in a modification to<br>
>> > > disable FastISel for non-darwin targets, or is it likely to be fixed<br>
>> > > quickly?<br>
>> > ><br>
>> > ><br>
>> > ><br>
>> > > -Gordon<br>
>> > ><br>
>> > ><br>
>> > > _______________________________________________<br>
>> > > LLVM Developers mailing list<br>
>> > > <a href="mailto:LLVMdev@cs.uiuc.edu" target="_blank">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
>> > > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
>> > ><br>
>><br>
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>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
><br>
><br>
><br>
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<br>
<br>
<br>
</div></div><span><font color="#888888">--<br>
With best regards, Anton Korobeynikov<br>
Faculty of Mathematics and Mechanics, Saint Petersburg State University<br>
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