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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">Here is a bit more data.<br>
After <font color="#000000" face="Tahoma" size="2">PrescheduleNodesWithMultipleUses has been run, the following
</font>Predecessor/Successor links are 'dumpAll'ed.<br>
(I attach the full dumpAll before & after "Prescheduling SU #7 next to PredSU #4 to guide scheduling in the presence of multiple uses")<br>
<br>
SU(3)<br>
Predecessors:<br>
val SU(5): Latency=1<br>
ch SU(7): Latency=1<br>
val SU(7): Latency=1<br>
<br>
SU(7):<br>
ch SU(3): Latency=1<br>
val SU(3): Latency=1<br>
val SU(5): Latency=1<br>
<br>
It looks odd but seems to be fine as all nodes are capable of being scheduled viz:<br>
<br>
NumSuccsLeft after each schedule<br>
sched - 0 2 1 3 5 7 6 8 4<br>
SU(0) 0 <br>
SU(1) 1 0<br>
SU(2) 1 0<br>
SU(3) 3 2 1 0<br>
SU(4) 1 0<br>
SU(5) 1 0<br>
SU(6) 1 0<br>
SU(7) 3 1 0<br>
SU(8) 1 0<br>
<br>
So, the problem comes back to trying to find the physical address of a 'CallResource' in the later part of PickNodeToScheduleBottomUp().<br>
<br>
Robert<br>
<br>
<br>
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<div style="direction: ltr;" id="divRpF449166"><font color="#000000" face="Tahoma" size="2"><b>From:</b> llvmdev-bounces@cs.uiuc.edu [llvmdev-bounces@cs.uiuc.edu] on behalf of Robert Lytton [robert@xmos.com]<br>
<b>Sent:</b> 20 August 2013 22:57<br>
<b>To:</b> llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> [LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???<br>
</font><br>
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<div style="direction:ltr; font-family:Tahoma; color:#000000; font-size:10pt">Hi,
<br>
<br>
I have an assert firing due to PickNodeToScheduleBottomUp():<br>
1. having a CallResource in use pushing an interference of current SUnit.<br>
2. having no more SUnits in the AvailableQueue<br>
3. The only interference being the SUnit that just failed due to a Call Resource.<br>
4. An attempt to duplicate this node which has the 'Call Resource' as a physical register.<br>
Thus the call to getMinimalPhysRegClass() asserts - Call Resource is not in a class!<br>
..../lib/CodeGen/TargetRegisterInfo.cpp:120: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const: Assertion `BestRC && "Couldn't find the register class"' failed.<br>
<br>
<br>
The interesting thing about this failure is that the Predecessor/Successor of two nodes was changed by PrescheduleNodesWithMultipleUses().<br>
If they were not, the AvailableQueue would have had nodes, and all would have been fine.<br>
I am quite uneasy over how PrescheduleNodesWithMultipleUses() has changed the Predecessor/Successor.<br>
It seems to have changed the DAG into something impossible to schedule - I need to look more carefully to confirm this.<br>
<br>
<br>
I'm not sure if this is one problem or two - or a target problem passing something dangerous to the scheduler.<br>
Any help would be most welcome.<br>
<br>
<br>
I have attached the code to exercise the bug - the slightest of perturbation will make it compile fine e.g. add an extra 'undef' argument to f2 viz: double @f2(i32, double, double, double).<br>
This example only fails for xcore targets.<br>
<br>
Robert<br>
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