<div dir="ltr"><div><div><div><div><div><div><br></div>Thanks for the information, allow maybe I can re-phrase the question or issue.<br><br>Assume 64-bit register types, but integer is 32-bit. Already have table generation of the 64-bit operation descriptions.<br>
<br></div>How about this modified approach?<br><br></div>Before type-legalization, I'd really like to move all MUL I64 to a subroutine call of my own choice.<br><br></div>This would be a form of customization, but I want this to happen before type legalization. Right now, type legalization, promotes all MUL I32 to 64-bit, and I lose the ability to differentiate between what originally<br>
was a MUL on 64-bit and 32-bit values.<br><br>Only thing that I have seen happen at DAG Selection is for lowering custom intrinsic functions like memcpy:<br><br>./Target/X86/X86SelectionDAGInfo.cpp:178:X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG,<br>
<br></div>Is there a general SelectionDAG conversion that can be made to happen before all type promotions?<br><br></div>Again, even modifications in ISelDAGToDAG.cpp will be after type promotion in my understanding.<br><div>
<div><br><br><div><div><div><br></div></div></div></div></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Jul 30, 2013 at 1:55 PM, Tom Stellard <span dir="ltr"><<a href="mailto:tom@stellard.net" target="_blank">tom@stellard.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On Tue, Jul 30, 2013 at 01:14:16PM -0600, Dan wrote:<br>
> I'll try to run through the scenario:<br>
><br>
><br>
> 64-bit register type target (all registers have 64 bits).<br>
><br>
> all 32-bits are getting promoted to 64-bit integers<br>
><br>
> Problem:<br>
><br>
> MUL on i32 is getting promoted to MUL on i64<br>
><br>
> MUL on i64 is getting expanded to a library call in compiler-rt<br>
><br>
><br>
<br>
</div>Can you fix this by marking i64 MUL as Legal?<br>
<div class="im"><br>
> the problem is that MUL32 gets promoted and then converted into a<br>
> subroutine call because it is now type i64, even though I want the MUL I32<br>
> to remain as an operation in the architecture. MUL i32 would generate a<br>
> 64-bit results from the lower 32-bit portions of 64-bit source operands.<br>
><br>
> In customize for the operations, I am trying to do something like:<br>
><br>
> case ISD::MUL:<br>
> {<br>
> EVT OpVT = Op.getValueType();<br>
> if (OpVT == MVT::i64) {<br>
> RTLIB::Libcall LC = RTLIB::MUL_I64;<br>
> SDValue Dummy;<br>
> return ExpandLibCall(LC, Op, DAG, false, Dummy, *this);<br>
> }<br>
> else if (OpVT == MVT::i32){<br>
><br>
> ??? What to do here to not have issues with type i32<br>
> }<br>
> }<br>
><br>
><br>
> I've gone a few directions on this.<br>
><br>
> Defining the architecture type i32 leads to a lot of changes that I don't<br>
> think is the most straightforward change.<br>
><br>
<br>
</div>When you say 'defining an architecture type' do you mean with<br>
addRegisterClass() in your TargetLowering constructor? If so, then this<br>
would be my recommendation. Can you elaborate more on what is<br>
preventing you from doing this.<br>
<div class="im"><br>
> Would think there is a way to promote the MUL i32 types but still be able<br>
> to "see" that as a MUL i32 somewhere down the lowering process.<br>
><br>
<br>
</div>The R600 backend does something similar to this. It has 24-bit MUL and<br>
MAD instructions and selects these by looking at an i32 integer and<br>
trying to infer whether or not it is really a 24-bit value.<br>
See the SelectI24 and SelectU24 functions in AMDGPUISelDAGToDAG.cpp.<br>
<br>
-Tom<br>
<div class="im"><br>
<br>
> Are there suggestions on how to promote the type, but then be able to<br>
> customize the original i64 to a call and the original mul i32 to an<br>
> operation?<br>
<br>
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<br>
</blockquote></div><br></div>