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<div class="moz-cite-prefix">On 07/14/2013 10:19 AM, Linus Torvalds
wrote:<br>
</div>
<blockquote
cite="mid:CA+55aFwKQQtTrgm7O8MLkqGgno-CsLSTM8tjrjuGmmqPEAZghw@mail.gmail.com"
type="cite">
<pre wrap="">Now, there are possible cases where you want to make the size explicit
because you are mixing memory operand sizes and there can be nasty
performance implications of doing a 32-bit write and then doing a
64-bit read of the result. I'm not actually aware of us having ever
worried/cared about it, but it's a possible source of trouble: mixing
bitop instructions with non-bitop instructions can have some subtle
interactions, and you need to be careful, since the size of the
operand affects both the offset *and* the memory access size.</pre>
</blockquote>
The SDM entry for BT mentions that the instruction may touch 2 or 4
bytes depending on the operand size, but doesn't specifically
mention that a 64 bit operation size touches 8 bytes - and it
doesn't mention anything at all about operand size and access size
in BTR/BTS/BTC (unless it's implied as part of the discussion about
encoding the MSBs of a constant bit offset in the offset of the
addressing mode). Is that an oversight?<br>
<br>
<blockquote
cite="mid:CA+55aFwKQQtTrgm7O8MLkqGgno-CsLSTM8tjrjuGmmqPEAZghw@mail.gmail.com"
type="cite">
<pre wrap=""> The
access size generally is meaningless from a semantic standpoint
(little-endian being the only sane model), but the access size *can*
have performance implications for the write queue forwarding.</pre>
</blockquote>
<br>
It looks like that if the base address isn't aligned then neither is
the generated access, so you could get a protection fault if it
overlaps a page boundary, which is a semantic rather than purely
operational difference.<br>
<blockquote>J<br>
</blockquote>
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