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<DIV>Yes your absolutely right, the Opcode and the Operands in each machine
instruction are sufficient to generate the final binary representation of the
MachineInstruction but not exactly. If you take a look at the format of each
MIPS instruction, you’ll see that there are some fixed bits for each instruction
which are not available inside the machine instruction object –From what I saw
so far-. Furthermore, how will I know how to map each operand to its right place
i.e. rt, rd, rs, immediate, offset, etc.., without knowing the semantic of the
instruction and the physical numbering of each register, to finally generate the
complete 32-bit encoding.</DIV>
<DIV> </DIV>
<DIV>MachineInstr::getOpcode() for a register operand returns an enum value that
doesn’t represent the actual physical numbering of the register, to know what
register this returned value represents I should refer to
MipsGenRegisterInfo.td, that’s where I think the mapping happens.</DIV>
<DIV> </DIV>
<DIV>However, inside the MipsCodeEmitter class there is a method that returns
the binary encoding of the machine instruction (uint64_t
MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why
I thought about activating the code emitter during post-ra would solve my
problem if that’s even possible.</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> - Jafar J.</DIV>
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<DIV style="font-color: black"><B>From:</B> <A title=grosbach@apple.com
href="mailto:grosbach@apple.com">Jim Grosbach</A> </DIV>
<DIV><B>Sent:</B> Thursday, May 30, 2013 8:49 PM</DIV>
<DIV><B>To:</B> <A title=pluck90@hotmail.com
href="mailto:pluck90@hotmail.com">Jafar J</A> </DIV>
<DIV><B>Cc:</B> <A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A> ; <A
title=llvmdev@cs.uiuc.edu href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A>
</DIV>
<DIV><B>Subject:</B> Re: [LLVMdev] Activating MIPS Code
Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
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<DIV> </DIV>
<DIV> </DIV>Thanks, that helps. The code emitter is definitely not the way
you want to go about solving this problem, though. Are the instruction opcode
(MachineInstr::getOpcode()) and the operand values not sufficient? All the
information present in the encoding should be inferable from those, as that’s
where the encoding comes from.
<DIV> </DIV>
<DIV>-Jim<BR>
<DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>
<DIV> </DIV>
<DIV>
<DIV>On May 30, 2013, at 10:12 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>> wrote:</DIV><BR
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size=3 face=Calibri>I need to represent each instruction with its (32-bit)
binary encoding, and I reached to a conclusion that I could get the encoding
through the MipsCodeEmitter. What I’m trying to do exactly is write a
scheduler which tries to minimize the switching activity between the scheduled
instructions in each basic block. One way to do that is by representing each
instruction with its complete binary encoding, which will be available after
the register allocation.</FONT></DIV></DIV>
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<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">Thanks
for the reply!</DIV></DIV>
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<DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">-Jafar
J</DIV>
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<DIV><FONT size=3 face=Calibri></FONT> </DIV>
<DIV style="BACKGROUND-COLOR: rgb(245,245,245)">
<DIV><B>From:</B><SPAN class=Apple-converted-space> </SPAN><A
title=grosbach@apple.com href="mailto:grosbach@apple.com">Jim
Grosbach</A></DIV>
<DIV><B>Sent:</B><SPAN class=Apple-converted-space> </SPAN>Thursday, May
30, 2013 7:55 PM</DIV>
<DIV><B>To:</B><SPAN class=Apple-converted-space> </SPAN><A
title=pluck90@hotmail.com href="mailto:pluck90@hotmail.com">Jafar J</A></DIV>
<DIV><B>Cc:</B><SPAN class=Apple-converted-space> </SPAN><A
title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A><SPAN
class=Apple-converted-space> </SPAN>;<SPAN
class=Apple-converted-space> </SPAN><A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A></DIV>
<DIV><B>Subject:</B><SPAN class=Apple-converted-space> </SPAN>Re:
[LLVMdev] Activating MIPS Code Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">What
are you actually trying to do? The code emitters have nothing to do with the
post-RA scheduler.
<DIV> </DIV>
<DIV>-Jim</DIV>
<DIV>
<DIV> </DIV>
<DIV>
<DIV>On May 30, 2013, at 6:23 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>> wrote:</DIV><BR
class=Apple-interchange-newline>
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<DIV>Hello,</DIV>
<DIV> </DIV>
<DIV> Is it possible to activate the MIPS code emitter
during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and
JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler
I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the
MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it
in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter
during PostRA Scheduler or am I missing something here.</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> Jafar
J.</DIV></DIV></DIV>_______________________________________________<BR>LLVM
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<DIV> </DIV></DIV></DIV></DIV></DIV>_______________________________________________<BR>LLVM
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