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<DIV>I’ve heard about removing the CodeEmitter Pass and replacing it with the
MCCodeEmitter, but I decided to stick with the current version I’m using.
Anyway, I really appreciate the help. I think I’ll have to think of another
solution.</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> - Jafar J.</DIV>
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<DIV style="font-color: black"><B>From:</B> <A title=grosbach@apple.com
href="mailto:grosbach@apple.com">Jim Grosbach</A> </DIV>
<DIV><B>Sent:</B> Thursday, May 30, 2013 10:44 PM</DIV>
<DIV><B>To:</B> <A title=pluck90@hotmail.com
href="mailto:pluck90@hotmail.com">Jafar J</A> </DIV>
<DIV><B>Cc:</B> <A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A> ; <A
title=llvmdev@cs.uiuc.edu href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A>
</DIV>
<DIV><B>Subject:</B> Re: [LLVMdev] Activating MIPS Code
Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
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style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: 'Calibri'; COLOR: #000000; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">
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<DIV>
<DIV>On May 30, 2013, at 11:35 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>> wrote:</DIV><BR
class=Apple-interchange-newline>
<BLOCKQUOTE type="cite">
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<DIV>Hi Jim,</DIV>
<DIV> </DIV>
<DIV>The idea of reducing the switching activity between the instructions
works by reducing the hamming distance between tow consecutive binary strings
across the basic block, or reducing the number of the different bits between
two consecutive instructions. This is why I need the exact complete encoding
in plain 0’s and 1’s, to be as precise as possible during the scheduling
process. I did write a class that generates a complete binary encoding from a
MachineInstruction, which took a while to do, but then I thought what if I
needed to target other processors such as ARM, then I’ll have to do the same
thing all over again knowing that the code emitter could get the job done.
Isn’t that the job of the code emitter converting the MachineInstruction to
machine code through the tableGen which has the definition of each
instruction. Isn’t it possible to just activate the code emitter during
Post-RA scheduler.</DIV>
<DIV> </DIV></DIV></DIV></DIV></BLOCKQUOTE>
<DIV> </DIV>No. Two reasons that’s not going to work. First, the
CodeEmitter runs as the absolute last pass. Nothing will ever come after it, and
it assumes that to be true (it’s for the JIT). Second, the CodeEmitter pass is
going away entirely sooner rather than later. The MCCodeEmitter takes its place.
That requires lowering the instructions to MC, which again happens much later,
and is required to happen much later, than the scheduler.</DIV>
<DIV> </DIV>
<DIV>-Jim</DIV>
<DIV><BR>
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<DIV>Sorry for the trouble!</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> Jafar J.</DIV>
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<DIV style="BACKGROUND-COLOR: rgb(245,245,245)">
<DIV><B>From:</B><SPAN class=Apple-converted-space> </SPAN><A
title=grosbach@apple.com href="mailto:grosbach@apple.com">Jim
Grosbach</A></DIV>
<DIV><B>Sent:</B><SPAN class=Apple-converted-space> </SPAN>Thursday, May
30, 2013 9:18 PM</DIV>
<DIV><B>To:</B><SPAN class=Apple-converted-space> </SPAN><A
title=pluck90@hotmail.com href="mailto:pluck90@hotmail.com">Jafar J</A></DIV>
<DIV><B>Cc:</B><SPAN class=Apple-converted-space> </SPAN><A
title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A><SPAN
class=Apple-converted-space> </SPAN>;<SPAN
class=Apple-converted-space> </SPAN><A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A></DIV>
<DIV><B>Subject:</B><SPAN class=Apple-converted-space> </SPAN>Re:
[LLVMdev] Activating MIPS Code Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">Hi
Jafar,
<DIV> </DIV>
<DIV>That’s not quite what I meant. Why do you need to know the exact encoding
at all? The instruction opcode+operands should have all the semantic
information you need without ever looking at the actual encoding.</DIV>
<DIV> </DIV>
<DIV>-Jim</DIV>
<DIV>
<DIV> </DIV>
<DIV>
<DIV>On May 30, 2013, at 11:08 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>> wrote:</DIV><BR
class=Apple-interchange-newline>
<BLOCKQUOTE type="cite">
<DIV
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<DIV>Yes your absolutely right, the Opcode and the Operands in each machine
instruction are sufficient to generate the final binary representation of
the MachineInstruction but not exactly. If you take a look at the format of
each MIPS instruction, you’ll see that there are some fixed bits for each
instruction which are not available inside the machine instruction object
–From what I saw so far-. Furthermore, how will I know how to map each
operand to its right place i.e. rt, rd, rs, immediate, offset, etc..,
without knowing the semantic of the instruction and the physical numbering
of each register, to finally generate the complete 32-bit encoding.</DIV>
<DIV> </DIV>
<DIV>MachineInstr::getOpcode() for a register operand returns an enum value
that doesn’t represent the actual physical numbering of the register, to
know what register this returned value represents I should refer to
MipsGenRegisterInfo.td, that’s where I think the mapping happens.</DIV>
<DIV> </DIV>
<DIV>However, inside the MipsCodeEmitter class there is a method that
returns the binary encoding of the machine instruction (uint64_t
MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s
why I thought about activating the code emitter during post-ra would solve
my problem if that’s even possible.</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> - Jafar J.</DIV>
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style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">
<DIV style="FONT: 10pt tahoma">
<DIV><FONT size=3 face=Calibri></FONT> </DIV>
<DIV style="BACKGROUND-COLOR: rgb(245,245,245)">
<DIV><B>From:</B><SPAN class=Apple-converted-space> </SPAN><A
title=grosbach@apple.com href="mailto:grosbach@apple.com">Jim
Grosbach</A></DIV>
<DIV><B>Sent:</B><SPAN class=Apple-converted-space> </SPAN>Thursday,
May 30, 2013 8:49 PM</DIV>
<DIV><B>To:</B><SPAN class=Apple-converted-space> </SPAN><A
title=pluck90@hotmail.com href="mailto:pluck90@hotmail.com">Jafar
J</A></DIV>
<DIV><B>Cc:</B><SPAN class=Apple-converted-space> </SPAN><A
title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A><SPAN
class=Apple-converted-space> </SPAN>;<SPAN
class=Apple-converted-space> </SPAN><A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A></DIV>
<DIV><B>Subject:</B><SPAN class=Apple-converted-space> </SPAN>Re:
[LLVMdev] Activating MIPS Code Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">
<DIV> </DIV>
<DIV> </DIV>Thanks, that helps. The code emitter is definitely not the
way you want to go about solving this problem, though. Are the instruction
opcode (MachineInstr::getOpcode()) and the operand values not sufficient?
All the information present in the encoding should be inferable from those,
as that’s where the encoding comes from.
<DIV> </DIV>
<DIV>-Jim<BR>
<DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>
<DIV> </DIV>
<DIV>
<DIV>On May 30, 2013, at 10:12 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>>
wrote:</DIV><BR class=Apple-interchange-newline>
<BLOCKQUOTE type="cite">
<DIV
style="TEXT-TRANSFORM: none; TEXT-INDENT: 0px; WORD-WRAP: break-word; WHITE-SPACE: normal; LETTER-SPACING: normal; WORD-SPACING: 0px; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; -webkit-text-stroke-width: 0px"
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<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none"><FONT
size=3 face=Calibri>I need to represent each instruction with its (32-bit)
binary encoding, and I reached to a conclusion that I could get the
encoding through the MipsCodeEmitter. What I’m trying to do exactly is
write a scheduler which tries to minimize the switching activity between
the scheduled instructions in each basic block. One way to do that is by
representing each instruction with its complete binary encoding, which
will be available after the register allocation.</FONT></DIV></DIV>
<DIV>
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<DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">Thanks
for the reply!</DIV></DIV>
<DIV>
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style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none"> </DIV></DIV>
<DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">-Jafar
J</DIV>
<DIV style="FONT: 10pt tahoma">
<DIV><FONT size=3 face=Calibri></FONT> </DIV>
<DIV style="BACKGROUND-COLOR: rgb(245,245,245)">
<DIV><B>From:</B><SPAN class=Apple-converted-space> </SPAN><A
title=grosbach@apple.com href="mailto:grosbach@apple.com">Jim
Grosbach</A></DIV>
<DIV><B>Sent:</B><SPAN class=Apple-converted-space> </SPAN>Thursday,
May 30, 2013 7:55 PM</DIV>
<DIV><B>To:</B><SPAN class=Apple-converted-space> </SPAN><A
title=pluck90@hotmail.com href="mailto:pluck90@hotmail.com">Jafar
J</A></DIV>
<DIV><B>Cc:</B><SPAN class=Apple-converted-space> </SPAN><A
title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</A><SPAN
class=Apple-converted-space> </SPAN>;<SPAN
class=Apple-converted-space> </SPAN><A title=llvmdev@cs.uiuc.edu
href="mailto:llvmdev@cs.uiuc.edu">Mailing List</A></DIV>
<DIV><B>Subject:</B><SPAN class=Apple-converted-space> </SPAN>Re:
[LLVMdev] Activating MIPS Code Emitter.</DIV></DIV></DIV>
<DIV> </DIV></DIV>
<DIV
style="FONT-STYLE: normal; DISPLAY: inline; FONT-FAMILY: calibri; FONT-SIZE: small; FONT-WEIGHT: normal; TEXT-DECORATION: none">What
are you actually trying to do? The code emitters have nothing to do with
the post-RA scheduler.
<DIV> </DIV>
<DIV>-Jim</DIV>
<DIV>
<DIV> </DIV>
<DIV>
<DIV>On May 30, 2013, at 6:23 AM, Jafar J <<A
href="mailto:pluck90@hotmail.com">pluck90@hotmail.com</A>>
wrote:</DIV><BR class=Apple-interchange-newline>
<BLOCKQUOTE type="cite">
<DIV
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<DIV style="FONT-FAMILY: calibri; FONT-SIZE: 12pt">
<DIV>Hello,</DIV>
<DIV></DIV>
<DIV> Is it possible to activate the MIPS code emitter
during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and
JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the
compiler I get an error that says
“/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error:
MipsGenRegisterInfo.inc file not found”. I’m assuming that the
MipsGenRegisterInfo.inc is not yet generated when I’m trying to include
it in the PostRAScheduler. Is this the way to activate the
mipsCodeEmitter during PostRA Scheduler or am I missing something
here.</DIV>
<DIV> </DIV>
<DIV>Thanks,</DIV>
<DIV> Jafar
J.</DIV></DIV></DIV>_______________________________________________<BR>LLVM
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