<p dir="ltr">Hi Mihail,</p>
<p dir="ltr">> Here is a practical example: ARM NEON vector instructions may work in either double word mode (taking d registers) or in quad word mode (taking q registers). The mode is selected by bit 6 (Q bit). When Q == 1, then quad word mode is used.<br>
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> There is an additional constraint: whenever Q == 1, the registers encoded in the instruction need to be even. Otherwise the encoding is undefined. <br>
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> This constraint is currently unimplemented and triggers incorrect behaviour in the MC disassembler. In order to correct this I would have to create custom decoder methods for a dozen-some instructions which is wasteful. I would much prefer to be able to define a constraint function like:</p>
<p dir="ltr">Actually, in this case don't you just have to add another check to DecodeQPRRegisterClass? It currently completely ignores the least-significant bit of its field, but should probably check that it's 0.</p>
<p dir="ltr">Or are there instructions that permit that bit to vary without actually affecting anything? I'm not aware of any, but if so the best solution is probably to create a second RegisterOperand class to handle this disparity and migrate some instructions over to it.</p>
<p dir="ltr">Cheers.</p>
<p dir="ltr">Tim.</p>