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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I agree. Take a look at the ARM backend instructions which operate on 2x32-bit registers as a 64 bit output. Look at things marked TwoOperandAliasConstraint in the tablegen files to see how they do this. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-Gordon<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Quentin Colombet<br><b>Sent:</b> Monday, April 15, 2013 6:00 PM<br><b>To:</b> Francois Pichet<br><b>Cc:</b> LLVM Developers Mailing List<br><b>Subject:</b> Re: [LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Using bundles here looks like a fragile way to handle that, IMHO.<o:p></o:p></p><div><p class=MsoNormal>Really, using a pseudo instruction seems the best approach for you.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>For instance, you can match your add64 during isel with your pseudo instruction and expand it just before emitting the assembly file (add a pass using the hook: addPreEmitPass on your target).<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-size:13.5pt;font-family:"Helvetica","sans-serif";color:black'>-Quentin<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Apr 15, 2013, at 2:37 PM, Francois Pichet <<a href="mailto:pichet2000@gmail.com">pichet2000@gmail.com</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><br>I really have to force them to stuck together otherwise the carry will just not work.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>How about wrapping the 2 instructions in a bundle?<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Would that be a way?<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><a href="http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles">http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles</a><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>On Mon, Apr 15, 2013 at 5:24 PM, Quentin Colombet<span class=apple-converted-space> </span><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>><span class=apple-converted-space> </span>wrote:<o:p></o:p></span></p><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Hi Francois,<o:p></o:p></span></p><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>If you model the effect of your carry on the instructions, the scheduler (and the other backend passes) should ensure that nothing that affects the carry will be inserted between your two instructions (assuming they are issued with nothing affecting the carry in between in the first place).<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Therefore, you shouldn’t have to force them to be stuck together.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>If you still do, what Jakob proposed is what you are looking for.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p><div><div><p class=MsoNormal><span style='font-size:13.5pt;font-family:"Helvetica","sans-serif"'>-Quentin<o:p></o:p></span></p></div></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p><div><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>On Apr 15, 2013, at 2:02 PM, Francois Pichet <<a href="mailto:pichet2000@gmail.com" target="_blank">pichet2000@gmail.com</a>> wrote:<o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Hi,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Instructions are defined as follow in TableGen:<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'> defm ADD64 : ALU32<"add", 1, 1, addc>;<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'> defm ADD64C : ALU32<"addrc", 1, 2, adde>;<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.<o:p></o:p></span></p></div><div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Is there a default guarantee that nothing will ever be inserted between "add" and "addrc" or is there a flag/condition to set somewhere to have that guarantee?<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>Thanks<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><o:p> </o:p></span></p></div></div></div></div></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu" target="_blank">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu/" target="_blank">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></span></p></div></blockquote></div></div></div></div></div></div><p class=MsoNormal><o:p> </o:p></p></div></div></div></body></html>