<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Apr 25, 2013, at 10:03 AM, Ulrich Weigand <<a href="mailto:Ulrich.Weigand@de.ibm.com">Ulrich.Weigand@de.ibm.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Jakob Stoklund Olesen <<a href="mailto:stoklund@2pi.dk">stoklund@2pi.dk</a>> wrote on 25.04.2013 18:58:05:<br><br><blockquote type="cite">On Apr 25, 2013, at 4:44 AM, Ulrich Weigand <<a href="mailto:Ulrich.Weigand@de.ibm.com">Ulrich.Weigand@de.ibm.com</a>><br></blockquote>wrote:<br><blockquote type="cite"><br><blockquote type="cite">Jakob Stoklund Olesen <<a href="mailto:stoklund@2pi.dk">stoklund@2pi.dk</a>> wrote on 24.04.2013 23:47:54:<br><br><blockquote type="cite">I would like to add one more case here: Fixed register operands.<br><br>Some instructions, like x86's MUL and DIV, take operands in fixed<br>registers. Currently, we handle that with COPY instructions to and<br>from the fixed registers, but that is making code motion passes more<br>complicated than they need to be. (Actually, they usually just run<br>away when they see one of these instructions).<br><br>I would like to have MUL32r take two virtual register operands, one<br>of them tied to the fixed register %EAX. Just like two-address<br>instructions, it would be the register allocator's responsibility to<br>satisfy the constraint. This would also make it possible to write<br>proper isel patterns for MUL and DIV.<br></blockquote><br>I'm wondering: is is not possible to handle this case by using a<br>register class containing just the one register?<br></blockquote><br>I think that would work too. Either way, you get MI operands that<br>aren't encoded.<br></blockquote><br>Right. Well, in any case this would also seem to argue for the rule<br>I suggested in my other email: the MC operand list should consist of<br>exactly those operands that are named in the AsmString.<br><br></div></blockquote><div><br></div><div>Perhaps we could/should have tablegen collect singleton registers like this and auto-generate the singleton register classes, instruction operands, etc? There might need to be some syntax in the (ins) and (outs) lists, too? Unclear. In general, I like being able to write instructions like this in the naive way and have tblgen figure out the rest.</div><div><br></div><div>-Jim</div></div></body></html>