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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I am experimenting with creating instructions that write into virtual registers that use the ARM GPRPair register class in Pre-RA phase.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>During register allocation, I hit an assertion because the code is not in SSA form:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>lib/CodeGen/MachineRegisterInfo.cpp:271: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || llvm::next(I) == def_end()) && "getVRegDef assumes a single definition or no definition"' failed.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The code in lib\CodeGen\MachineRegisterInfo.cpp has information about the virtual register’s sub-register been written, but that info is not propagated to getVRegDef.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Is it possible/ is there any plan to update the code analysis to distinguish virtual register’s sub-registers definitions? So that GPRPair sub-registers can be used by instructions that do not return 64 bit value?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Example:<o:p></o:p></p><p class=MsoNormal>This is a simple example of machine instructions I caused to be generated. I forced the LDRi12 instructions to use a GPRPair sub-register.<o:p></o:p></p><p class=MsoNormal>The copy into %vreg4 asserts because of the two definitions of vreg9, coming from vreg9:gsub_0 and vreg9:gsub_1.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal> %vreg1<def> = COPY %R1; GPR:%vreg1<o:p></o:p></p><p class=MsoNormal> %vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2<o:p></o:p></p><p class=MsoNormal> %vreg3<def> = ADDrsi %vreg2<kill>, %vreg1, 18, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg3,%vreg2,%vreg1<o:p></o:p></p><p class=MsoNormal> %vreg9:gsub_0<def,read-undef> = LDRi12 %vreg3, 112, pred:14, pred:%noreg; mem:LD4[%arrayidx83](tbaa=!"int") GPRPair:%vreg9 :%vreg3<o:p></o:p></p><p class=MsoNormal> %vreg9:gsub_1<def,read-undef> = LDRi12 %vreg3, 116, pred:14, pred:%noreg; mem:LD4[%arrayidx86](tbaa=!"int") GPRPair:%vreg9 :%vreg3<o:p></o:p></p><p class=MsoNormal> %vreg4<def> = COPY %vreg9:gsub_0; GPR:%vreg4 GPRPair:%vreg9<o:p></o:p></p><p class=MsoNormal> %vreg5<def> = COPY %vreg9:gsub_1; GPR:%vreg5 GPRPair:%vreg9<o:p></o:p></p><p class=MsoNormal> %vreg6<def> = LDRi12 %vreg3, 120, pred:14, pred:%noreg; mem:LD4[%arrayidx89](tbaa=!"int") GPR:%vreg6,%vreg3<o:p></o:p></p><p class=MsoNormal> %vreg7<def> = ADDrr %vreg4<kill>, %vreg5<kill>, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg7,%vreg4,%vreg5<o:p></o:p></p><p class=MsoNormal> %vreg8<def> = ADDrr %vreg7<kill>, %vreg6<kill>, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg8,%vreg7,%vreg6<o:p></o:p></p><p class=MsoNormal> %R0<def> = COPY %vreg8; GPR:%vreg8<o:p></o:p></p><p class=MsoNormal> BX_RET pred:14, pred:%noreg, %R0<imp-use><o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<br>Ana.<o:p></o:p></p></div></body></html>