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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I sent a patch to llvm-commits for this issue. Please help to review it.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/168354.html<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Eric Christopher [mailto:echristo@gmail.com] <br><b>Sent:</b> Wednesday, March 13, 2013 1:15 PM<br><b>To:</b> Måns Rullgård<br><b>Cc:</b> Jim Grosbach; Zhao; LLVM Dev<br><b>Subject:</b> Re: [LLVMdev] Problems with 64-bit register operands of inline asm on ARM<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>On Wed, Mar 13, 2013 at 1:04 PM, Måns Rullgård <<a href="mailto:mans@mansr.com" target="_blank">mans@mansr.com</a>> wrote:<o:p></o:p></p><div><div><p class=MsoNormal style='margin-bottom:12.0pt'>Jim Grosbach <<a href="mailto:grosbach@apple.com">grosbach@apple.com</a>> writes:<br><br>> On Mar 13, 2013, at 11:21 AM, Måns Rullgård <<a href="mailto:mans@mansr.com">mans@mansr.com</a>> wrote:<br>><br>>> Jim Grosbach <<a href="mailto:grosbach@apple.com">grosbach@apple.com</a>> writes:<br>>><br>>>> On Mar 13, 2013, at 11:01 AM, Renato Golin <<a href="mailto:renato.golin@linaro.org">renato.golin@linaro.org</a>><br>>>> wrote:<br>>>><br>>>>> On 13 March 2013 17:57, Jim Grosbach <<a href="mailto:grosbach@apple.com">grosbach@apple.com</a>> wrote:<br>>>>>> It seems to me that LLVM doesn’t parse the inline asm body. It just<br>>>>>> checks the constraints, (ie. Input/output interface). During ASM<br>>>>>> writing, it then binding those constraints to placeholders like %0,<br>>>>>> %1.<br>>>>> This is correct.<br>>>>><br>>>>> Ok, so maybe checking all possible ways to require paired registers<br>>>>> is not such a bad idea after all.<br>>>>><br>>>><br>>>> The constraints are the right way to do it. There shouldn't be any<br>>>> magic beyond that.<br>>><br>>> Since there is no special operand constraint for a register pair, there<br>>> is no way to tell at that level.<br>>><br>>> GCC has (implicitly) defined 64-bit register operands as residing in<br>>> even/odd pairs, thus leaving inline asm free to make all manner of<br>>> assumptions based on this. The only way I see to guarantee<br>>> compatibility is to mimic the gcc behaviour here. It may be slightly<br>>> suboptimal in a few cases, but it's the safe choice.<br>><br>> Sure, that's fine for ARM mode. No realistic other option there. So<br>> long as Thumb2 code can get the more expressive syntax for the more<br>> relaxed regalloc availability, it's all good. This basically falls<br>> into "using the constraints to figure it out."<o:p></o:p></p></div></div><p class=MsoNormal>So let's at least make this pair allocation unconditional in ARM mode.<br>A lot of existing inline asm doesn't work in Thumb mode anyway, so if<br>that fails, it's less of an issue.<o:p></o:p></p><div><div><p class=MsoNormal><o:p> </o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I can agree with this. Bugged me last time I was looking at it too.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>-eric <o:p></o:p></p></div></div></div></div></div></body></html>