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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jim Grosbach [mailto:grosbach@apple.com] <br><b>Sent:</b> Wednesday, March 13, 2013 10:57 AM<br><b>To:</b> weimingz@codeaurora.org; Zhao<br><b>Cc:</b> Renato Golin; Måns Rullgård; LLVM Dev<br><b>Subject:</b> Re: [LLVMdev] Problems with 64-bit register operands of inline asm on ARM<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Mar 13, 2013, at 10:15 AM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Renato,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>It seems to me that LLVM doesn’t parse the inline asm body. It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1. </span><o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>This is correct.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>So it a constraint is a 64-integer type, it *<b>probably</b>* needs paired GPR.</span><o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>This is not. Consider the Thumb2 encodings of LDRD, LDREXD, etc,, for example. They allow arbitrary Rt and Rt2, not just a register pair. It's only in ARM mode that the instructions are more constrained.<o:p></o:p></p></div><div><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>(Exactly. That’s why I say “probably needs” :D )<o:p></o:p></span></p></div><div><p class=MsoNormal>-Jim<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Weiming</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span class=apple-converted-space><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> </span></span><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>Renato Golin [<a href="mailto:renato.golin@linaro.org">mailto:renato.golin@linaro.org</a>]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Wednesday, March 13, 2013 10:03 AM<br><b>To:</b><span class=apple-converted-space> </span>Måns Rullgård<br><b>Cc:</b><span class=apple-converted-space> </span>LLVM Dev; <a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a><br><b>Subject:</b><span class=apple-converted-space> </span>Re: Problems with 64-bit register operands of inline asm on ARM</span><o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><p class=MsoNormal>On 13 March 2013 13:43, Måns Rullgård <<a href="mailto:mans@mansr.com" target="_blank"><span style='color:purple'>mans@mansr.com</span></a>> wrote:<o:p></o:p></p></div><div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'><div><p class=MsoNormal>One possible fix, which I have tested, is to look for the specific<br>instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in<br>addition to the 'H' modifier. However, there are probably other<br>creative ways in which inline asm might rely on the specific pairing.<o:p></o:p></p></div></blockquote><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Hi Mans,<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have something better than just grep for possible extensions for paired registers.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'><div><p class=MsoNormal>Thus I believe the safest solution is to always force 64-bit operands<br>into even/odd pairs for any inline asm. In other words, we should<br>probably do something like this (untested):<o:p></o:p></p></div></blockquote><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>I tested this, and it fails on other inline assembly tests. I think that the non-paired asm is correctly selected by the table generated parser, but when you pair things that didn't need pairing, the parser goes bad.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>I don't think we should force pairing on every inline assembly either. Maybe someone knows how to parse inline assembly in a better way than it is currently being done? If there isn't any, than possibly creating a function to return "needsPairedRegister()" or something would still be ugly, but better than incrementing it inline.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>cheers,<o:p></o:p></p></div></div><div><div><p class=MsoNormal>--renato<o:p></o:p></p></div></div></div></div><p class=MsoNormal>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></p></div></div><p class=MsoNormal><o:p> </o:p></p></div></body></html>