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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi David,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Your point is correct, I guess then vmlx-forwarding attribute needs to be revisited, since it is on by default for Cortex-A9. So far on codes I’m looking at (not only MILC), it always a win to disable it for Cortex-A9. In any case, I’m speaking about scalar (not vector) fp (not integer) operations, that’s why I would like a way to selectively enable it for such kind of operations only.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Best Regards<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Seb<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> David Tweed [mailto:david.tweed@arm.com] <br><b>Sent:</b> Monday, February 11, 2013 5:46 PM<br><b>To:</b> 'Renato Golin'; Sebastien DELDON-GNB<br><b>Cc:</b> llvmdev@cs.uiuc.edu<br><b>Subject:</b> RE: [LLVMdev] Is there any llvm neon intrinsic that maps to vmla.f32 instruction ?<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><div><div><div><div><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>Hi,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'>| </span><span lang=EN-GB>If we find that this optimization produces worse code in more cases than not, than we should leave it disable by default and let the user enable when necessary. I'll let Bob follow up on that, since I don't know what benchmarks he used.<o:p></o:p></span></p></div><div><p class=MsoNormal><span lang=EN-GB style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Note that it may well be the case that the most "generally performant" default may vary between different ARM cores as well as various types of code. It would certainly be as well to try benchmarking on different cores. as theoretical discussion of which code sequence is better is often add odds with empirically observed results.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Cheers,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Dave<o:p></o:p></span></p></div></div></div></div></div></div></body></html>