I have an llvm ir, which generates the following machine code using llc (llvm 3.0 on win32) after # *** IR Dump After X86 DAG->DAG Instruction Selection ***:<div><br><div>The first three lines and the last two lines alone together are used to compute "sin" for some double number.</div>
<div><br></div><div>- line 1: move the stack pointer down 8</div><div>- line 2: copy the updated stack pointer to a base register</div><div>- line 3: copy a double number to location pointed by the base register</div><div>
<br></div><div>- line end-1: to the last call "sin" to compute the result</div><div>- line end: move the stack pointer up 8</div><div><br></div><div>The problem is that there are many other instructions inserted between them, and these instructions include stack allocations. This causes:</div>
<div><br></div><div>1. "sin" function gets the wrong value to compute because the stack pointer moves and wrong value is received.</div><div>2. the function call after line end could get wrong values because after line end the stack pointer is pointing to useful data.</div>
<div><br></div><div>Could anyone working on x86 instruction selection give some pointers to prevent this?</div><div><br></div><div>Thanks,</div><div>-Peng</div><div><br></div><div><br></div><div><div><span class="Apple-tab-span" style="white-space:pre"> </span>ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg; mem:LD8[%85] FR64:%vreg190</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg191<def> = MOVSDrm <fi#0>, 1, %noreg, 96, %noreg; mem:LD8[%87] FR64:%vreg191</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg192<def> = MOVSDrm <fi#0>, 1, %noreg, 88, %noreg; mem:LD8[%92] FR64:%vreg192</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg193<def> = MOVSDrm <fi#0>, 1, %noreg, 24, %noreg; mem:LD8[%89] FR64:%vreg193</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg194<def> = MOVSDrm <fi#0>, 1, %noreg, 80, %noreg; mem:LD8[%94] FR64:%vreg194</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg195<def> = MOV32ri 8; GR32:%vreg195</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%EAX<def> = COPY %vreg195; GR32:%vreg195</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg196<def> = COPY %ESP; GR32:%vreg196</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOV32mr %vreg196, 1, %noreg, 0, %noreg, %vreg16; mem:ST4[%114] GR32:%vreg196,%vreg16</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg197<def> = MOV32ri 72; GR32:%vreg197</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%EAX<def> = COPY %vreg197; GR32:%vreg197</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use></div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg198<def> = COPY %ESP; GR32:%vreg198</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 56, %noreg, %vreg194; mem:ST8[%116+56] GR32:%vreg198 FR64:%vreg194</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 64, %noreg, %vreg17; mem:ST8[%116+64] GR32:%vreg198 FR64:%vreg17</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 48, %noreg, %vreg192; mem:ST8[%116+48] GR32:%vreg198 FR64:%vreg192</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 32, %noreg, %vreg191; mem:ST8[%116+32] GR32:%vreg198 FR64:%vreg191</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 24, %noreg, %vreg36; mem:ST8[%116+24] GR32:%vreg198 FR64:%vreg36</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 16, %noreg, %vreg190; mem:ST8[%116+16] GR32:%vreg198 FR64:%vreg190</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 8, %noreg, %vreg190; mem:ST8[%116+8] GR32:%vreg198 FR64:%vreg190</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 0, %noreg, %vreg190; mem:ST8[%116] GR32:%vreg198 FR64:%vreg190</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg199<def> = MOVSDrm %noreg, 1, %noreg, <cp#4>, %noreg; mem:LD8[ConstantPool](align=16) FR64:%vreg199</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg200<def> = FsXORPDrr %vreg193, %vreg199; FR64:%vreg200,%vreg193,%vreg199</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOVSDmr %vreg198, 1, %noreg, 40, %noreg, %vreg200; mem:ST8[%116+40] GR32:%vreg198 FR64:%vreg200</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg201<def> = MOV32ri 16; GR32:%vreg201</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%EAX<def> = COPY %vreg201; GR32:%vreg201</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>%vreg202<def> = COPY %ESP; GR32:%vreg202</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOV32mr %vreg202, 1, %noreg, 8, %noreg, %vreg19; mem:ST4[%118+8] GR32:%vreg202,%vreg19</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>MOV32mr %vreg202, 1, %noreg, 4, %noreg, %vreg18; mem:ST4[%118+4] GR32:%vreg202,%vreg18</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>MOV32mr %vreg202, 1, %noreg, 0, %noreg, %vreg0; mem:ST4[%118] GR32:%vreg202,%vreg0</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>CALLpcrel32 <es:sin>, %EAX<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>, ... ; line end-1</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>ADJCALLSTACKUP32 8, 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line end</div></div>
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