<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Jan 23, 2013, at 3:45 PM, ryan baird <<a href="mailto:ryanrbaird@gmail.com">ryanrbaird@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">I was reading about the order of optimizations in the code generation stage here: <a href="http://llvm.org/docs/CodeGenerator.html#the-high-level-design-of-the-code-generator">http://llvm.org/docs/CodeGenerator.html#the-high-level-design-of-the-code-generator</a><br>
<br>This is the part that's interesting to me:<br><br>3. <a class="reference internal" href="http://llvm.org/docs/CodeGenerator.html#ssa-based-machine-code-optimizations">SSA-based Machine Code Optimizations</a> — This optional stage consists of a
series of machine-code optimizations that operate on the SSA-form produced by
the instruction selector. Optimizations like<b> modulo-scheduling</b> or peephole
optimization work here.<br>4. <a class="reference internal" href="http://llvm.org/docs/CodeGenerator.html#register-allocation">Register Allocation</a> — The target code is transformed from an infinite
virtual register file in SSA form to the concrete register file used by the
target. This phase<b> introduces spill code</b> and eliminates all virtual register
references from the program.<br><br>If modulo scheduling happens before more code is introduced, how do we know that we still have an optimal schedule? Is there another scheduling stage during later optimization?<br></blockquote><div><br></div><div>There is a post-RA scheduling pass. It is only used when compiling for in-order CPUs. Out-of-order CPUs usually don't care.</div><div><br></div><div>/jakob</div><div><br></div></div></body></html>