<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Nov 26, 2012, at 9:43 AM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:</div><blockquote type="cite"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex; position: static; z-index: auto; "><br></blockquote><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex; position: static; z-index: auto; ">Of course, while writing this, I just realized this is a variant of a<br>
bug which has been discussed on llvm-commits: PR13622. And gcc<br>
actually does implement pairs on x86; I think the choice of registers<br>
is based on some internal register allocator sequence. And gcc also<br>
knows how to allocate register triplets on x86 (though I have no clue<br>
how you would use them). :)<br>
<br>
Ugh, I wish gcc's inline asm extension didn't expose so much of the<br>
insanity of gcc internals.<br></blockquote><div><br></div><div>Yes, inline assembly that exposes register allocation details is pretty annoying.</div><div><br></div><div>Jakob: Thoughts on how you'd want to model this as it goes through the allocator?</div></div></div></blockquote><div><br></div><div>The allocator wants all constraints expressed as register classes. Even-odd pairs of consecutive registers should be modeled as pseudo-registers. This is what Weiming is currently working on for ARM register pairs using the new GPRPair register class. (Feel free to review his patch from 11/19).</div><div><br></div><div>However, a pair of registers that don't constrain the register allocator should be modeled as two separate virtual registers.</div><div><br></div><div>So if GCC is using register pairs just to model an illegal type like i64 on ARM, the constraint should be handled by multiple virtual registers. If there are additional constraints on the register pair (e.g. they must be consecutive), the pair should be modeled as a single virtual register with sub-registers.</div><div><br></div><div>The INLINEASM MachineInstr already supports a single constraint mapping to multiple MachineOperands. X86 "m" constraints map to 5 operands, for example. A single "r" constraint should be able to map to multiple register operands as well.</div><div><br></div><div>/jakob</div><div><br></div></div></body></html>