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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu]
<b>On Behalf Of </b>Akira Hatanaka<br>
<b>Sent:</b> Thursday, September 06, 2012 5:47 PM<br>
<b>To:</b> Michael LIAO<br>
<b>Cc:</b> llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> Re: [LLVMdev] 64 bit special purpose registers<o:p></o:p></span></p>
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<p class="MsoNormal">On Thu, Sep 6, 2012 at 10:56 AM, Michael LIAO <<a href="mailto:michael.hliao@gmail.com" target="_blank">michael.hliao@gmail.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">On Thu, Sep 6, 2012 at 10:02 AM, Reed Kotler <<a href="mailto:rkotler@mips.com">rkotler@mips.com</a>> wrote:<br>
> Here is the problem explained more.<br>
><br>
> Normally there is a 64 bit register that is the result of certain multiply<br>
> and divide instructions.<br>
> It's really 2 32 bit registers.<br>
><br>
> This is like HI[0]/Lo[0]<br>
><br>
> In fact there are four such pairs, only the 0th pair available to basic<br>
> multiply and divide.<br>
><br>
> But DSP instructions have access to 4 , Hi[i],Lo[i], i=0..3<br>
><br>
> We want the register allocator to allocate them for us but also we need to<br>
> have them paired,<br>
> i.e. Hi[1],Lo[1]<o:p></o:p></p>
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<p class="MsoNormal">Sounds exactly the same as ARM to support double registers (pairing of<br>
2 float registers.). You may look into ARM for details.<o:p></o:p></p>
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><br>
> So in principle if you have a 64 bit register you can have two 32 bit<br>
> registers inside.<br>
><br>
> If you tell the register allocator that you have 64 bit registers, then it<br>
> wants to assume that 64 bit<br>
> is a legal operand type and then llvm assumes that you have native<br>
> instructions for all the 64 bit<br>
> types, and we don't have that in mips32, for example. So you would have to<br>
> lower them all yourself.<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">You can explicitly specify all of them as 'Expand' so LLVM will expand<br>
64-bit operation into 32-bit one.<o:p></o:p></p>
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<p class="MsoNormal"><br>
I am suspecting the code in SelectionDAGLegalize won't expand 64-bit operations to 32-bit ones. For example, I see this code in SelectionDAGLegalize::ExpandNode (near line 3090):<br>
<br>
case ISD::SUB: {<br>
EVT VT = Node->getValueType(0);<br>
assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&<br>
TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&<br>
"Don't know how to expand this subtraction!");<br>
<br>
<br>
If we mark the action of SUB, ADD and XOR as 'Expand', the code will assert.<br>
<br>
So you have to either make i64 illegal or mark the nodes as 'Custom' and write code to lower them.<o:p></o:p></p>
<p class="MsoNormal"><b><i><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">[Villmow, Micah] Or an alternate solution is to implement subtract in a sequence of smaller but legal subtractions.<o:p></o:p></span></i></b></p>
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<p class="MsoNormal"><span class="hoenzb"><span style="color:#888888">- Michael</span></span><o:p></o:p></p>
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<p class="MsoNormal"><br>
><br>
><br>
><br>
> On 09/06/2012 05:06 AM, Ivan Llopard wrote:<br>
><br>
> Hi Akira, Micah,<br>
><br>
> On 05/09/2012 21:44, Akira Hatanaka wrote:<br>
><br>
> Micah,<br>
><br>
> Do you mean we should make GPR64 available to register allocator by calling<br>
> addRegisterClass?<br>
><br>
> addRegisterClass(MVT::i64, &GPR64RegClass)<br>
><br>
><br>
> I have a related question to this thread. Does the RA use target lowering<br>
> information?<br>
> Because if it doesn't, you don't need to register your i64 reg class.<br>
><br>
> Ivan<br>
><br>
><br>
> If we add register class GPR64, type legalization will stop expanding i64<br>
> operations because i64 is now a legal type.<br>
> Then we will probably have to write lots of code to custom-lower unsupported<br>
> 64-bit operations during legalization. Note that mips32/16 lacks support for<br>
> most of the basic 64-bit instructions (add, sub, etc.).<br>
><br>
> I don't think setting operation action by calling setOperationAction(...<br>
> ,MVT::i64, Expand) would work either. Judging from the code I see in<br>
> Legalize.cpp, operation legalization doesn't seem to do much to expand<br>
> unsupported i64 operations.<br>
><br>
> On Tue, Aug 7, 2012 at 9:24 AM, Villmow, Micah <<a href="mailto:Micah.Villmow@amd.com">Micah.Villmow@amd.com</a>><br>
> wrote:<br>
>><br>
>> This can be done by declaring a register class with these registers and<br>
>> only using that register class as an operand in the instructions where it is<br>
>> legal.<br>
>> You then set as sub registers what you want to represent as the hi and lo<br>
>> registers for those 64bit registers.<br>
>><br>
>> So something like this:<br>
>> def lo_comp : SubRegIndex;<br>
>> def hi_comp : SubRegIndex;<br>
>> def R1 : Register<1>;<br>
>> def R2 : Register<2>;<br>
>> def R3 : Register<1>;<br>
>> def R4 : Register<2>;<br>
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;<br>
>><br>
>> This says that D1 is a register with two components, lo and hi. When you<br>
>> allocate D1, you also use R1/R2.<br>
>> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))><br>
>> ...<br>
>> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;<br>
>><br>
>> So in your instruction it would be something like:<br>
>> def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR32:$src1), ...>;<br>
>><br>
>> This would mean you take in two inputs and you have 64bit output. When D1<br>
>> is not being used, R1/R2 will get allocated to instructions that use GPR32<br>
>> register class, otherwise they will be seen as used and not get allocated.<br>
>><br>
>> Hope this helps,<br>
>> Micah<br>
>><br>
>> > -----Original Message-----<br>
>> > From: <a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>]<br>
>> > On Behalf Of reed kotler<br>
>> > Sent: Monday, August 06, 2012 4:52 PM<br>
>> > To: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
>> > Subject: [LLVMdev] 64 bit special purpose registers<br>
>> ><br>
>> > On Mips 32 there is traditionally a 64 bit HI/LO register for the result<br>
>> > of multiplying two 64 bit numbers.<br>
>> ><br>
>> > There are corresponding instructions to load the LO and HI parts into<br>
>> > individual 32 registers.<br>
>> ><br>
>> > On Mips with the DSP ASE (an application specific extension), there are<br>
>> > actual 4 such pairs of registers.<br>
>> ><br>
>> > Is there a way to have special purpose 64 bit registers without actually<br>
>> > having to tell LLVM that you have a 64 bit processor?<br>
>> ><br>
>> > But it's still possible to use the individual parts of the 64 register<br>
>> > as temporaries.<br>
>> ><br>
>> > The only true 64 bit operation is multiplying two 32 bit numbers.<br>
>> ><br>
>> ><br>
>> > _______________________________________________<br>
>> > LLVM Developers mailing list<br>
>> > <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">
http://llvm.cs.uiuc.edu</a><br>
>> > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
>><br>
>><br>
>><br>
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