<html>
<head>
<meta content="text/html; charset=ISO-8859-1"
http-equiv="Content-Type">
</head>
<body bgcolor="#FFFFFF" text="#000000">
<div class="moz-cite-prefix">Here is the problem explained more.<br>
<br>
Normally there is a 64 bit register that is the result of certain
multiply and divide instructions.<br>
It's really 2 32 bit registers.<br>
<br>
This is like HI[0]/Lo[0]<br>
<br>
In fact there are four such pairs, only the 0th pair available to
basic multiply and divide.<br>
<br>
But DSP instructions have access to 4 , Hi[i],Lo[i], i=0..3<br>
<br>
We want the register allocator to allocate them for us but also we
need to have them paired,<br>
i.e. Hi[1],Lo[1]<br>
<br>
So in principle if you have a 64 bit register you can have two 32
bit registers inside.<br>
<br>
If you tell the register allocator that you have 64 bit registers,
then it wants to assume that 64 bit<br>
is a legal operand type and then llvm assumes that you have native
instructions for all the 64 bit<br>
types, and we don't have that in mips32, for example. So you would
have to lower them all yourself.<br>
<br>
<br>
On 09/06/2012 05:06 AM, Ivan Llopard wrote:<br>
</div>
<blockquote cite="mid:504891B0.6080900@gmail.com" type="cite">
<meta http-equiv="Content-Type" content="text/html;
charset=ISO-8859-1">
Hi Akira, Micah,<br>
<br>
On 05/09/2012 21:44, Akira Hatanaka wrote:<br>
<blockquote
cite="mid:CAB297Qzqd6PMy4yNYBhzoRvYQ10RDJPMnJUnUtw0B2PDCwOE1Q@mail.gmail.com"
type="cite">Micah,<br>
<br>
Do you mean we should make GPR64 available to register allocator
by calling addRegisterClass?<br>
<br>
addRegisterClass(MVT::i64, &GPR64RegClass)<br>
</blockquote>
<br>
I have a related question to this thread. Does the RA use target
lowering information?<br>
Because if it doesn't, you don't need to register your i64 reg
class.<br>
<br>
Ivan<br>
<br>
<blockquote
cite="mid:CAB297Qzqd6PMy4yNYBhzoRvYQ10RDJPMnJUnUtw0B2PDCwOE1Q@mail.gmail.com"
type="cite"><br>
If we add register class GPR64, type legalization will stop
expanding i64 operations because i64 is now a legal type.<br>
Then we will probably have to write lots of code to custom-lower
unsupported 64-bit operations during legalization. Note that
mips32/16 lacks support for most of the basic 64-bit
instructions (add, sub, etc.).<br>
<br>
I don't think setting operation action by calling
setOperationAction(... ,MVT::i64, Expand) would work either.
Judging from the code I see in Legalize.cpp, operation
legalization doesn't seem to do much to expand unsupported i64
operations.<br>
<br>
<div class="gmail_quote">On Tue, Aug 7, 2012 at 9:24 AM,
Villmow, Micah <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:Micah.Villmow@amd.com" target="_blank">Micah.Villmow@amd.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex"> This can
be done by declaring a register class with these registers
and only using that register class as an operand in the
instructions where it is legal.<br>
You then set as sub registers what you want to represent as
the hi and lo registers for those 64bit registers.<br>
<br>
So something like this:<br>
def lo_comp : SubRegIndex;<br>
def hi_comp : SubRegIndex;<br>
def R1 : Register<1>;<br>
def R2 : Register<2>;<br>
def R3 : Register<1>;<br>
def R4 : Register<2>;<br>
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp,
hi_comp]>;<br>
<br>
This says that D1 is a register with two components, lo and
hi. When you allocate D1, you also use R1/R2.<br>
def GPR32 : RegisterClass<..., [i32], [32], (add
(sequence "R%u", 1, 4))> ...<br>
def GPR64 : RegisterClass<..., [i64], [64], (add D1)>
...;<br>
<br>
So in your instruction it would be something like:<br>
def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0,
GPR32:$src1), ...>;<br>
<br>
This would mean you take in two inputs and you have 64bit
output. When D1 is not being used, R1/R2 will get allocated
to instructions that use GPR32 register class, otherwise
they will be seen as used and not get allocated.<br>
<br>
Hope this helps,<br>
Micah<br>
<div class="HOEnZb">
<div class="h5"><br>
> -----Original Message-----<br>
> From: <a moz-do-not-send="true"
href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>
[mailto:<a moz-do-not-send="true"
href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>]<br>
> On Behalf Of reed kotler<br>
> Sent: Monday, August 06, 2012 4:52 PM<br>
> To: <a moz-do-not-send="true"
href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
> Subject: [LLVMdev] 64 bit special purpose registers<br>
><br>
> On Mips 32 there is traditionally a 64 bit HI/LO
register for the result<br>
> of multiplying two 64 bit numbers.<br>
><br>
> There are corresponding instructions to load the LO
and HI parts into<br>
> individual 32 registers.<br>
><br>
> On Mips with the DSP ASE (an application specific
extension), there are<br>
> actual 4 such pairs of registers.<br>
><br>
> Is there a way to have special purpose 64 bit
registers without actually<br>
> having to tell LLVM that you have a 64 bit
processor?<br>
><br>
> But it's still possible to use the individual parts
of the 64 register<br>
> as temporaries.<br>
><br>
> The only true 64 bit operation is multiplying two
32 bit numbers.<br>
><br>
><br>
> _______________________________________________<br>
> LLVM Developers mailing list<br>
> <a moz-do-not-send="true"
href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a>
<a moz-do-not-send="true"
href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> <a moz-do-not-send="true"
href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev"
target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
<br>
<br>
<br>
_______________________________________________<br>
LLVM Developers mailing list<br>
<a moz-do-not-send="true"
href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a>
<a moz-do-not-send="true"
href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
<a moz-do-not-send="true"
href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev"
target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
</div>
</div>
</blockquote>
</div>
<br>
<br>
<fieldset class="mimeAttachmentHeader"></fieldset>
<br>
<pre wrap="">_______________________________________________
LLVM Developers mailing list
<a moz-do-not-send="true" class="moz-txt-link-abbreviated" href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a moz-do-not-send="true" class="moz-txt-link-freetext" href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a>
<a moz-do-not-send="true" class="moz-txt-link-freetext" href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a>
</pre>
</blockquote>
<br>
<br>
<fieldset class="mimeAttachmentHeader"></fieldset>
<br>
<pre wrap="">_______________________________________________
LLVM Developers mailing list
<a class="moz-txt-link-abbreviated" href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a class="moz-txt-link-freetext" href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a>
<a class="moz-txt-link-freetext" href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a>
</pre>
</blockquote>
<br>
</body>
</html>