<br><br>On Thursday, September 6, 2012, Akira Hatanaka wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">If no i64 reg classes are registered, then type-legalization will expand a 32b x 32b = 64b multiply node into a 32-bit mult node with two i32 results (for example, SMUL_LOHI). The problem is that there isn't an easy way to have RA assign two consecutive hi/lo registers to the two i32 registers, once the 64-bit result is split into two 32-bit results.<br>
<br>Is there a constraint I can use (something like register hints) to force RA to allocate consecutive registers? <br></blockquote><div><br></div><div>No. RA has no such constraints. I once hacked similar issue (i.e. some data type has very limited support or special usage at processor level) by registering register class after computeRegisterProperties(). This way you won't tell SelectionDAG i64 is a legal type but only an available type at machine level. Ofc, you need very special code emitter to emit SMUL_LOHI into your MUL followed by subreg extractions. Anyway,it once worked for me but may not be a desired approach.</div>
<div><br></div><div>- michael</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br><div>On Thu, Sep 6, 2012 at 5:06 AM, Ivan Llopard <span dir="ltr"><<a>ivanllopard@gmail.com</a>></span> wrote:<br>
<blockquote style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
Hi Akira, Micah,<div><br>
<br>
On 05/09/2012 21:44, Akira Hatanaka wrote:<br>
<blockquote type="cite">Micah,<br>
<br>
Do you mean we should make GPR64 available to register allocator
by calling addRegisterClass?<br>
<br>
addRegisterClass(MVT::i64, &GPR64RegClass)<br>
</blockquote>
<br></div>
I have a related question to this thread. Does the RA use target
lowering information?<br>
Because if it doesn't, you don't need to register your i64 reg
class.<span><font color="#888888"><br>
<br>
Ivan</font></span><div><div><br>
<br>
<blockquote type="cite"><br>
If we add register class GPR64, type legalization will stop
expanding i64 operations because i64 is now a legal type.<br>
Then we will probably have to write lots of code to custom-lower
unsupported 64-bit operations during legalization. Note that
mips32/16 lacks support for most of the basic 64-bit instructions
(add, sub, etc.).<br>
<br>
I don't think setting operation action by calling
setOperationAction(... ,MVT::i64, Expand) would work either.
Judging from the code I see in Legalize.cpp, operation
legalization doesn't seem to do much to expand unsupported i64
operations.<br>
<br>
<div>On Tue, Aug 7, 2012 at 9:24 AM, Villmow,
Micah <span dir="ltr"><<a>Micah.Villmow@amd.com</a>></span>
wrote:<br>
<blockquote style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
This can be done by declaring a register class with these
registers and only using that register class as an operand in
the instructions where it is legal.<br>
You then set as sub registers what you want to represent as
the hi and lo registers for those 64bit registers.<br>
<br>
So something like this:<br>
def lo_comp : SubRegIndex;<br>
def hi_comp : SubRegIndex;<br>
def R1 : Register<1>;<br>
def R2 : Register<2>;<br>
def R3 : Register<1>;<br>
def R4 : Register<2>;<br>
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp,
hi_comp]>;<br>
<br>
This says that D1 is a register with two components, lo and
hi. When you allocate D1, you also use R1/R2.<br>
def GPR32 : RegisterClass<..., [i32], [32], (add (sequence
"R%u", 1, 4))> ...<br>
def GPR64 : RegisterClass<..., [i64], [64], (add D1)>
...;<br>
<br>
So in your instruction it would be something like:<br>
def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0,
GPR32:$src1), ...>;<br>
<br>
This would mean you take in two inputs and you have 64bit
output. When D1 is not being used, R1/R2 will get allocated to
instructions that use GPR32 register class, otherwise they
will be seen as used and not get allocated.<br>
<br>
Hope this helps,<br>
Micah<br>
<div>
<div><br>
> -----Original Message-----<br>
> From: <a>llvmdev-bounces@cs.uiuc.edu</a>
[mailto:<a>llvmdev-bounces@cs.uiuc.edu</a>]<br>
> On Behalf Of reed kotler<br>
> Sent: Monday, August 06, 2012 4:52 PM<br>
> To: <a>llvmdev@cs.uiuc.edu</a><br>
> Subject: [LLVMdev] 64 bit special purpose registers<br>
><br>
> On Mips 32 there is traditionally a 64 bit HI/LO
register for the result<br>
> of multiplying two 64 bit numbers.<br>
><br>
> There are corresponding instructions to load the LO
and HI parts into<br>
> individual 32 registers.<br>
><br>
> On Mips with the DSP ASE (an application specific
extension), there are<br>
> actual 4 such pairs of registers.<br>
><br>
> Is there a way to have special purpose 64 bit
registers without actually<br></div></div></blockquote></div></blockquote></div></div></div></blockquote></div></blockquote>