How about vector parameters?<br><br>define internal fastcc <4 x float> @add(<4 x float> %a.val, <4 x float> %b.val) nounwind {<br>entry:<br> %tmp4 = fadd <4 x float> %a.val, %b.val<br> ret <4 x float> %tmp4<br>
}<br><br><br>a and b are flattened by SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) before letting the target handle it.<br><br> SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),<br>
F.isVarArg(), Ins,<br> dl, DAG, InVals);<br><br>The "Ins" have all the parameters flattened to primitive types. I would like the vector parameters to be lowered using vector registers. <br>
<br><br><div class="gmail_quote">On Tue, Sep 4, 2012 at 11:35 AM, Krzysztof Parzyszek <span dir="ltr"><<a href="mailto:kparzysz@codeaurora.org" target="_blank">kparzysz@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="im">On 9/4/2012 11:16 AM, Khaled Mohammed wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Is there an option to do sret demotion via a register? if yes, do we<br>
have a Target to see an example implementation?<br>
</blockquote>
<br></div>
Hi Khaled,<br>
<br>
Check out X86TargetLowering::<u></u>LowerReturn, and the call to getSRetReturnReg.<br>
<br>
The SRetReturnReg looks like a hack (each target that uses it, declares this variable individually), but that seems to be the current way of handling it.<span class="HOEnZb"><font color="#888888"><br>
<br>
-K<br>
<br>
-- <br>
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