<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<meta name="Generator" content="Microsoft Word 12 (filtered medium)">
<style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:Tahoma;
panose-1:2 11 6 4 3 5 4 4 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-reply;
font-family:"Calibri","sans-serif";
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
<body lang="EN-US" link="blue" vlink="purple">
<div class="WordSection1">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
<div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt">
<div>
<div style="border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Akira Hatanaka [mailto:ahatanak@gmail.com]
<br>
<b>Sent:</b> Wednesday, September 05, 2012 12:44 PM<br>
<b>To:</b> Villmow, Micah<br>
<b>Cc:</b> reed kotler; llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> Re: [LLVMdev] 64 bit special purpose registers<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">Micah,<br>
<br>
Do you mean we should make GPR64 available to register allocator by calling addRegisterClass?<br>
<br>
addRegisterClass(MVT::i64, &GPR64RegClass)<br>
<br>
If we add register class GPR64, type legalization will stop expanding i64 operations because i64 is now a legal type.<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt"><b><i><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">[Villmow, Micah] You'll have to set everything that you don't support to 'Expand' and everything you do support into 'Legal'.<o:p></o:p></span></i></b></p>
<p class="MsoNormal" style="margin-bottom:12.0pt"><br>
Then we will probably have to write lots of code to custom-lower unsupported 64-bit operations during legalization. Note that mips32/16 lacks support for most of the basic 64-bit instructions (add, sub, etc.).<br>
<br>
I don't think setting operation action by calling setOperationAction(... ,MVT::i64, Expand) would work either. Judging from the code I see in Legalize.cpp, operation legalization doesn't seem to do much to expand unsupported i64 operations.<o:p></o:p></p>
<div>
<p class="MsoNormal">On Tue, Aug 7, 2012 at 9:24 AM, Villmow, Micah <<a href="mailto:Micah.Villmow@amd.com" target="_blank">Micah.Villmow@amd.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">This can be done by declaring a register class with these registers and only using that register class as an operand in the instructions where it is legal.<br>
You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers.<br>
<br>
So something like this:<br>
def lo_comp : SubRegIndex;<br>
def hi_comp : SubRegIndex;<br>
def R1 : Register<1>;<br>
def R2 : Register<2>;<br>
def R3 : Register<1>;<br>
def R4 : Register<2>;<br>
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;<br>
<br>
This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/R2.<br>
def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> ...<br>
def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;<br>
<br>
So in your instruction it would be something like:<br>
def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR32:$src1), ...>;<br>
<br>
This would mean you take in two inputs and you have 64bit output. When D1 is not being used, R1/R2 will get allocated to instructions that use GPR32 register class, otherwise they will be seen as used and not get allocated.<br>
<br>
Hope this helps,<br>
Micah<o:p></o:p></p>
<div>
<div>
<p class="MsoNormal"><br>
> -----Original Message-----<br>
> From: <a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>]<br>
> On Behalf Of reed kotler<br>
> Sent: Monday, August 06, 2012 4:52 PM<br>
> To: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
> Subject: [LLVMdev] 64 bit special purpose registers<br>
><br>
> On Mips 32 there is traditionally a 64 bit HI/LO register for the result<br>
> of multiplying two 64 bit numbers.<br>
><br>
> There are corresponding instructions to load the LO and HI parts into<br>
> individual 32 registers.<br>
><br>
> On Mips with the DSP ASE (an application specific extension), there are<br>
> actual 4 such pairs of registers.<br>
><br>
> Is there a way to have special purpose 64 bit registers without actually<br>
> having to tell LLVM that you have a 64 bit processor?<br>
><br>
> But it's still possible to use the individual parts of the 64 register<br>
> as temporaries.<br>
><br>
> The only true 64 bit operation is multiplying two 32 bit numbers.<br>
><br>
><br>
> _______________________________________________<br>
> LLVM Developers mailing list<br>
> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">
http://llvm.cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
<br>
<br>
<br>
_______________________________________________<br>
LLVM Developers mailing list<br>
<a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">
http://llvm.cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></p>
</div>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
</div>
</body>
</html>