Hi Sergei,<div><br></div><div>I just fixed the broken test case for PR13719 with <span style="background-color:rgb(255,255,255);white-space:pre-wrap">r163107, but from the debugging output you've posted it suspect it won't fix your test case.</span></div>
<div><br></div><div><span style="background-color:rgb(255,255,255);white-space:pre-wrap">Your analysis looks good - findLastUseBefore(..) doesn't appear to be handling physregs. I'm surprised that isn't causing more failures. I'll see if I can find a failing case in the LLVM test-suite (it's been a while since I ran live-interval-update over all of it) and try out your modifications to findLastUseBefore.</span></div>
<div><span style="background-color:rgb(255,255,255);white-space:pre-wrap"><br></span></div><div><span style="background-color:rgb(255,255,255);white-space:pre-wrap">Thanks very much for all of your work on this. </span></div>
<div><span style="background-color:rgb(255,255,255);white-space:pre-wrap"><br></span></div><div><span style="background-color:rgb(255,255,255);white-space:pre-wrap">Cheers,</span></div><div><span style="background-color:rgb(255,255,255);white-space:pre-wrap">Lang.</span></div>
<div><br></div><div><div class="gmail_quote">On Sat, Sep 1, 2012 at 4:57 AM, Sergei Larin <span dir="ltr"><<a href="mailto:slarin@codeaurora.org" target="_blank">slarin@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-US" link="blue" vlink="purple"><div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Lang, <u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> I think I am getting closer to understanding this. The findLastUseBefore() should probably look something like this:<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">// Return the last use of reg between NewIdx and OldIdx.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {<u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> SlotIndex LastUse = NewIdx;<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {<u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> for (MCRegUnitRootIterator Roots(Reg, &TRI); Roots.isValid(); ++Roots) {<u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> unsigned Root = *Roots;<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> for (MachineRegisterInfo::use_nodbg_iterator<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI = MRI.use_nodbg_begin(Root),<u></u><u></u></span></p><div class="im"><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UE = MRI.use_nodbg_end();<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI != UE; UI.skipInstruction()) {<u></u><u></u></span></p>
</div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> const MachineInstr* MI = &*UI;<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> if (InstSlot > LastUse && InstSlot < OldIdx) <u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> LastUse = InstSlot;<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> }<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> //for (MCSuperRegIterator Supers(Root, &TRI); Supers.isValid(); ++Supers) <u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> // I do not think we should be doing this here…<u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> }<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> } else {<u></u><u></u></span></p>
<div class="im"><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> for (MachineRegisterInfo::use_nodbg_iterator<u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI = MRI.use_nodbg_begin(Reg),<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UE = MRI.use_nodbg_end();<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI != UE; UI.skipInstruction()) {<u></u><u></u></span></p></div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> const MachineInstr* MI = &*UI;<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> if (InstSlot > LastUse && InstSlot < OldIdx) <u></u><u></u></span></p><p class="MsoNormal">
<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> LastUse = InstSlot;<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> }<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> }<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> return LastUse;<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> }<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">This is not a patch, more like thinking aloud… If this does not make sense, please let me know.<u></u><u></u></span></p>
<div class="im"><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Sergei<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><div><p class="MsoNormal"><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d">---<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.5pt;font-family:"Calibri","sans-serif";color:#1f497d">Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d"><u></u><u></u></span></p>
</div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p></div><div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt">
<div><div style="border:none;border-top:solid #b5c4df 1.0pt;padding:3.0pt 0in 0in 0in"><p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> <a href="mailto:llvmdev-bounces@cs.uiuc.edu" target="_blank">llvmdev-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvmdev-bounces@cs.uiuc.edu" target="_blank">llvmdev-bounces@cs.uiuc.edu</a>] <b>On Behalf Of </b>Sergei Larin<br>
<b>Sent:</b> Friday, August 31, 2012 11:53 AM<br><b>To:</b> 'Lang Hames'<br><b>Cc:</b> 'LLVM Developers Mailing List'</span></p><div><div class="h5"><br><b>Subject:</b> Re: [LLVMdev] Assert in LiveInterval update<u></u><u></u></div>
</div><p></p></div></div><div><div class="h5"><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Hi Lang,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> Just one more quick question… in LiveIntervalAnalysis.cpp In <u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx)<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Did you really mean to use<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">for (MachineRegisterInfo::use_nodbg_iterator<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI = MRI.use_nodbg_begin(Reg),<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UE = MRI.use_nodbg_end();<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> UI != UE; UI.skipInstruction()) {}<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Aren’t we currently dealing with units, not registers ?<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">…and isn’t MRI.use_nodbg_begin(Reg) expects a register, not a unit? …or did I got it wrong again… Sorry to bug you on this.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Sergei<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d">---<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.5pt;font-family:"Calibri","sans-serif";color:#1f497d">Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p><div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt">
<div><div style="border:none;border-top:solid #b5c4df 1.0pt;padding:3.0pt 0in 0in 0in"><p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Lang Hames [<a href="mailto:lhames@gmail.com" target="_blank">mailto:lhames@gmail.com</a>] <br>
<b>Sent:</b> Thursday, August 30, 2012 3:17 PM<br><b>To:</b> Sergei Larin<br><b>Cc:</b> Andrew Trick; LLVM Developers Mailing List<br><b>Subject:</b> Re: [LLVMdev] Assert in LiveInterval update<u></u><u></u></span></p></div>
</div><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">Hi Sergei, Andy,<u></u><u></u></p><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">Sorry - I got distracted with some other work. I'm looking into this and PR13719 now. I'll let you know what I find out.<u></u><u></u></p>
</div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">Sergei - thanks very much for the investigation. That should help me pin this down.<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p>
</div><div><p class="MsoNormal">Cheers,<u></u><u></u></p></div><div><p class="MsoNormal">Lang.<u></u><u></u></p><div><p class="MsoNormal" style="margin-bottom:12.0pt"><u></u> <u></u></p><div><p class="MsoNormal">On Tue, Aug 28, 2012 at 2:33 PM, Sergei Larin <<a href="mailto:slarin@codeaurora.org" target="_blank">slarin@codeaurora.org</a>> wrote:<u></u><u></u></p>
<p class="MsoNormal">Andy, Lang,<br><br> Thanks for the suggestion.<br><br><br> I have spent more time with it today, and I do see some strange things in<br>liveness update. I am not at the actual cause yet, but here is what I got so<br>
far:<br><br>I have the following live ranges when I start scheduling a region:<br><br>R2 = [0B,48r:0)[352r,416r:5)...<br>R3 = [0B,48r:0)[368r,416r:5)...<br>R4 = [0B,32r:0)[384r,416r:4)...<br>R5 = [0B,32r:0)[400r,416r:4)...<br>
<br>I schedule the following instruction (48B):<br><br>0B BB#0: derived from LLVM BB %entry<br> Live Ins: %R0 %R1 %D1 %D2<br>8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27<br>12B %vreg30<def> = LDriw <fi#-1>, 0;<br>
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30<br>20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]<br>IntRegs:%vreg31<br>24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26<br>
28B %vreg106<def> = TFRI 16777216;<br>IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop<br>32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29<br>
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28<br><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B<br>
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]<br>IntRegs:%vreg37<br><br>In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.<br>The MI move triggers liveness update, which first triggers SlotIndex<br>
renumbering:<br><br>*** Renumbered SlotIndexes 24-56 ***<br><br>So my 48B becomes 56B, so after the update new live ranges look like this:<br><br>R2 = [0B,56r:0)[352r,416r:5)...<br>R3 = [0B,56r:0)[368r,416r:5)...<br>R4 = [0B,48r:0)[384r,416r:4)...<br>
R5 = [0B,48r:0)[400r,416r:4)...<br><br>Then in LiveIntervals::handleMove OldIndex 56B and NewIndex is 32B (also new<br>after renumbering. But happens to match another old one).<br>collectRanges for MI figures that it is moving a paired register, and<br>
correctly(?) selects these two ranges to update for %R2:R3<br><br>[0B,56r:0)[368r,416r:5)...<br>[0B,56r:0)[352r,416r:5)...<br><br>___BUT____ after the update, my new ranges look like this:<br><br>R2 = [0B,32r:0)[352r,416r:5)...<br>
R3 = [0B,48r:0)[368r,416r:5)...<<<<< Bogus range, 56r should have become 48r<br>R4 = [0B,48r:0)[384r,416r:4)...<br>R5 = [0B,48r:0)[400r,416r:4)...<br>....<br>0B BB#0: derived from LLVM BB %entry<br> Live Ins: %R0 %R1 %D1 %D2<br>
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27<br>12B %vreg30<def> = LDriw <fi#-1>, 0;<br>mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30<br>20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]<br>
IntRegs:%vreg31<br>24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26<br>32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28<br><<<<<<<<<<<<<<<< Moved instruction<br>
40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<br>48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29<br>96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]<br>
IntRegs:%vreg37<br><br>This is not caught at this time, and only much later, when another<br>instruction is scheduled to __the same slot___ the old one "occupied" (48B),<br>the discrepancy is caught by one of unrelated asserts... I think at that<br>
time there are simply some stale aliases in liveness table.<br><br>I'm going to continue with this tomorrow, but if this helps to identify a<br>lurking bug today, my day was worth it :) :) :)<u></u><u></u></p><div><p class="MsoNormal">
<br>Sergei<br><br>--<br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.<br><br><br>> -----Original Message-----<u></u><u></u></p></div><div><div><p class="MsoNormal">> From: Andrew Trick [mailto:<a href="mailto:atrick@apple.com" target="_blank">atrick@apple.com</a>]<br>
> Sent: Tuesday, August 28, 2012 3:47 PM<br>> To: Sergei Larin<br>> Cc: LLVM Developers Mailing List; Lang Hames<br>> Subject: Re: [LLVMdev] Assert in LiveInterval update<br>><br>> On Aug 28, 2012, at 8:18 AM, Sergei Larin <<a href="mailto:slarin@codeaurora.org" target="_blank">slarin@codeaurora.org</a>><br>
> wrote:<br>> ><br>> > I've described that issue (see below) when you were out of town... I<br>> > think I am getting more context on it. Please take a look...<br>> ><br>> > So, in short, when the new MI scheduler performs move of an<br>
> > instruction, it does something like this:<br>> ><br>> > // Move the instruction to its new location in the instruction<br>> stream.<br>> > MachineInstr *MI = SU->getInstr();<br>> ><br>
> > if (IsTopNode) {<br>> > assert(SU->isTopReady() && "node still has unscheduled<br>> dependencies");<br>> > if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<<< Here we<br>
> make<br>> > sure that CurrentTop != MI.<br>> > CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);<br>> > else {<br>> > moveInstruction(MI, CurrentTop);<br>> > TopRPTracker.setPos(MI);<br>
> > }<br>> > ...<br>> ><br>> > But in moveInstruction we use<br>> ><br>> > // Update the instruction stream.<br>> > BB->splice(InsertPos, BB, MI);<br>> ><br>> > And splice as far as I understand moves MI to the location right<br>
> > __before__ InsertPos. Our previous check made sure that InsertPos !=<br>> > MI, But I do hit a case, when MI == InsertPos--, and effectively<br>> tries<br>> > to swap instruction with itself... which make live update mechanism<br>
> very unhappy.<br>> ><br>> > If I am missing something in intended logic, please explain,<br>> otherwise<br>> > it looks like we need to adjust that check to make sure we never even<br>> > considering this situation (swapping with self).<br>
> ><br>> > I also wonder if we want explicit check in live update with more<br>> > meaningful assert :)<br>><br>> Thanks for debugging this! The code above assumes that you're moving an<br>> unscheduled instruction, which should never be above InsertPos for top-<br>
> down scheduling. If the instruction was in multiple ready Q's, then you<br>> may attempt to schedule it multiple times. You can avoid this by<br>> checking Su->isScheduled in your Strategy's pickNode. See<br>
> InstructionShuffler::pickNode for an example. I don't see an equivalent<br>> check in ConvergingScheduler, but there probably should be.<br>><br>> Another possibility to consider is something strange with DebugValues,<br>
> which I haven't tested much.<br>><br>> I reproduced the same assert on arm and filed PR13719. I'm not sure yet<br>> if it's exactly the same issue, but we can move the discussion there.<br>><br>
> We need a better assert in live update and probably the scheduler too.<br>> Lang mentioned he may look at the issue today. Meanwhile, I hope my<br>> suggestion above helps.<br>><br>> -Andy<br><br>_______________________________________________<br>
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