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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I’m wondering if LLVM plans to support paired register constraints for 64-bit data.<o:p></o:p></p><p class=MsoNormal>Take ARM for example, the atomic i64 value read/write instuctions: ldrexd/strexd, require aligned register pairs (even/odd). <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Currently, in LLVM ARM (ARMISelDAGToDAG.cpp), ldrexd/strexd get hard coded registers (R0,R1) before register allocation via intrinsic. <o:p></o:p></p><p class=MsoNormal>It would be neater if there is a register constraint and register class that support 64-bit data and let the reg allocator to select the available register pair.<o:p></o:p></p><p class=MsoNormal>More importantly, it can solve issues for inline asm that requires 64-bit data binding: inline asm won’t be treated as intrinsic so there is no guarantee to get paired registers.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<o:p></o:p></p><p class=MsoNormal>Weiming<o:p></o:p></p></div></body></html>