<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Jul 24, 2012, at 3:52 PM, Justin Holewinski <<a href="mailto:justin.holewinski@gmail.com">justin.holewinski@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div class="gmail_quote">On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <span dir="ltr"><<a href="mailto:thomas.stellard@amd.com" target="_blank">thomas.stellard@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5">On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote:<br>
> I'm starting to look into binary instruction encodings in TableGen, and I'm<br>
> a bit confused on how the instruction fields are populated. Perhaps I'm<br>
> just being dense, but I cannot see how SDAG operands are translated into<br>
> the encoding fields. Can someone please explain the following snippet from<br>
> the PPC back-end.<br>
><br>
> The AND instruction in PPC is defined as:<br>
><br>
> 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),<br>
> 1012 "and $rA, $rS, $rB", IntSimple,<br>
> 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;<br>
><br>
> Okay, so rA, rS, and rB are register operands.<br>
><br>
> The TableGen classes are defined as:<br>
><br>
> 315 class XForm_base_r3xo_swapped<br>
> 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,<br>
> 317 InstrItinClass itin><br>
> 318 : I<opcode, OOL, IOL, asmstr, itin> {<br>
> 319 bits<5> A;<br>
> 320 bits<5> RST;<br>
> 321 bits<5> B;<br>
> 322<br>
> 323 bit RC = 0; // set by isDOT<br>
><br>
> 324<br>
> 325 let Inst{6-10} = RST;<br>
> 326 let Inst{11-15} = A;<br>
> 327 let Inst{16-20} = B;<br>
> 328 let Inst{21-30} = xo;<br>
> 329 let Inst{31} = RC;<br>
> 330 }<br>
><br>
> 337 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string<br>
> asmstr,<br>
> 338 InstrItinClass itin, list<dag> pattern><br>
> 339 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {<br>
> 340 let Pattern = pattern;<br>
> 341 }<br>
><br>
> Okay, so A, RST, and B are the operand fields in the instruction encoding<br>
> (I assume). But where are A, RST, and B given values? When the<br>
> instruction is encoded (and the physical registers are known), where do<br>
> these values come from? A grep for RST doesn't come up with anything<br>
> useful. Is there C++ code somewhere that scans the operands of all<br>
> instructions and performs the actual encoding?<br>
><br>
<br>
</div></div>The getMachineOpValue() function does the encoding for the non-MC code<br>
emitter. The MC code emitter might be different though.<br></blockquote><div><br></div><div>Yeah, I see the calls to getMachineOpValue() in the generated code, but it seems like it just processes the fields of the TableGen class in the order that they appear, e.g. A, RST, B in the PPC example, which seems very fragile. This makes me believe I'm missing something here.</div>
<div> </div></div></blockquote><div><br></div><div>If the bitfields are named the same as the operands in the (ins) and (outs) lists, TableGen will match them that way rather than positionally. ARM makes extensive use of that, for example.</div><div><br></div><div>-Jim</div><div><br></div><br><blockquote type="cite"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex; position: static; z-index: auto; ">
<span class="HOEnZb"><font color="#888888"><br>
-Tom<br>
<br>
> --<br>
><br>
> Thanks,<br>
><br>
> Justin Holewinski<br>
<br>
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<br>
<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div><br>
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