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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>In our (NVIDIA’s) NVVM IR spec, we define i1 having a memory size of 8 bit. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> setOperationAction(ISD::LOAD, MVT::i1, Custom);<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> setOperationAction(ISD::STORE, MVT::i1, Custom);<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>is the right way to go.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Yuan<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Justin Holewinski<br><b>Sent:</b> Monday, July 02, 2012 9:55 AM<br><b>To:</b> Dmitry N. Mikushin<br><b>Cc:</b> llvmdev@cs.uiuc.edu<br><b>Subject:</b> Re: [LLVMdev] [NVPTX] Backend failure in LegalizeDAG due to unimplemented expand in target lowering<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Okay, few issues here:<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>First, i1 is used in the NVPTX back-end to map to the predicate (.pred) type. We definitely do not want to declare this type as illegal. The real issue is lack of complete support for this type. The PTX language places restrictions on what can be done with .pred registers, and it looks like the failure is here:<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><p class=MsoNormal><span style='font-family:"Courier New"'>kernelgen_hostcall.exit228: ; preds = %while.cond.i226</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Courier New"'> store i1 false, i1 addrspace(1)* undef, align 8</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Ignoring for a second that you're storing to an undefined address (???), the back-end does not yet handle up-casting an i1 to an appropriate type for storage. The memory space is not bit-addressable, so a direct store of an i1 does not make sense. In the short term, I would recommend that you manually zext from/to i8 and load/store those.<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Sun, Jul 1, 2012 at 10:14 AM, Dmitry N. Mikushin <<a href="mailto:maemarcus@gmail.com" target="_blank">maemarcus@gmail.com</a>> wrote:<o:p></o:p></p><p class=MsoNormal>Hi Duncan,<br><br>Sorry I don't understand your point, could you please explain a little bit more?<br>Why i1 should be declared illegal? Operations on byte-wide types like<br>char or bool are pretty legal, according to PTX spec:<br><br>"Registers may be typed (signed integer, unsigned integer, floating<br>point, predicate) or untyped. Register size is restricted; aside from<br>predicate registers which are 1-bit, scalar registers have a width of<br>8-, 16-, 32-, or 64-bits, and vector registers have a width of 16-,<br>32-, 64-, or 128-bits. The most common use of 8-bit registers is with<br>ld, st, and cvt instructions, or as elements of vector tuples."<br><br>Thanks,<br>- D.<o:p></o:p></p><div><div><p class=MsoNormal><br>2012/6/30 Duncan Sands <<a href="mailto:baldrick@free.fr">baldrick@free.fr</a>>:<br>> Hi Dmitry,<br>><br>>>> did you declare i1 to be an illegal type?<br>>><br>>><br>>> No. How?<br>><br>><br>> I think it will be considered illegal if you don't add it to any<br>> register class.<br>><br>> Ciao, Duncan.<br>><br>><br>>><br>>> 2012/6/30 Duncan Sands <<a href="mailto:baldrick@free.fr">baldrick@free.fr</a>>:<br>>>><br>>>> Hi Dmitry,<br>>>>><br>>>>> So instead of setOperationAction(ISD::STORE, MVT::i1, Expand); one<br>>>>> should probably do setOperationAction(ISD::STORE, MVT::i1, Custom);<br>>>>> and implement it in NVPTXTargetLowering::LowerOperation.<br>>>>><br>>>>> But this issue makes a good point about the code efficiency: I suspect<br>>>>> such expansion will be very ugly in terms of performance. Probably we<br>>>>> can do much better if bool would use i32 instead of i1. I don't know<br>>>>> how to do that, though. Is it possible?<br>>>><br>>>><br>>>> did you declare i1 to be an illegal type? If so, you shouldn't get any<br>>>> stores of i1 at this stage (you may get trunc stores to i1, but that is<br>>>> different).<br>>>><br>>>> Ciao, Duncan.<br>>>><br>>>>><br>>>>> Anyway, if this is a defect, then it's a blocker for us, and we'd much<br>>>>> appreciate a fix.<br>>>>><br>>>>> - D.<br>>>>><br>>>>> 2012/6/29 Eli Friedman <<a href="mailto:eli.friedman@gmail.com">eli.friedman@gmail.com</a>>:<br>>>>>><br>>>>>> On Fri, Jun 29, 2012 at 2:11 PM, Dmitry N. Mikushin<br>>>>>> <<a href="mailto:maemarcus@gmail.com">maemarcus@gmail.com</a>> wrote:<br>>>>>>><br>>>>>>> Hi again,<br>>>>>>><br>>>>>>> Kind people on #llvm helped me to utilize bugpoint to reduce the<br>>>>>>> previously submitted test case. For record, it code be done with the<br>>>>>>> following command:<br>>>>>>><br>>>>>>> $ bugpoint -llc-safe test.ll<br>>>>>>><br>>>>>>> The resulting IR is attached, and it is crashing in the same way. Is<br>>>>>>> it a valid code?<br>>>>>><br>>>>>><br>>>>>> Looks like a bug in the NVPTXISelLowering.cpp: it has<br>>>>>> "setOperationAction(ISD::STORE, MVT::i1, Expand);", but the legalizer<br>>>>>> doesn't know how to handle that.<br>>>>>><br>>>>>> -Eli<br>>>>><br>>>>> _______________________________________________<br>>>>> LLVM Developers mailing list<br>>>>> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>>>>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>>>>><br>>>><br>>>><br>>>> _______________________________________________<br>>>> LLVM Developers mailing list<br>>>> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>>>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>><br>><br>><br><br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></p></div></div></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal style='margin-bottom:12.0pt'>-- <o:p></o:p></p><div><p class=MsoNormal>Thanks,<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Justin Holewinski<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p></div></div>
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