Machine Function
********** REWRITING TWO-ADDR INSTRS **********
********** Function: test
	%vreg3<earlyclobber,def>, %vreg4<earlyclobber,def,dead>, %vreg5<earlyclobber,def,dead> = nextsample@IFF %vreg2<kill>; int:%vreg3,%vreg2 float:%vreg4,%vreg5
		prepend:	%vreg3<def> = COPY %vreg2; int:%vreg3,%vreg2
		rewrite to:	%vreg3<earlyclobber,def>, %vreg4<earlyclobber,def,dead>, %vreg5<earlyclobber,def,dead> = nextsample@IFF %vreg3; int:%vreg3 float:%vreg4,%vreg5
********** PROCESS IMPLICIT DEFS **********
********** Function: test
0 
16 %vreg13<def> = COPY %cuI2<kill>; int:%vreg13
32 %vreg11<def> = COPY %cuI1<kill>; int:%vreg11
48 %vreg8<def> = COPY %cuI0<kill>; int:%vreg8
64 %vreg0<def> = COPY %vI254; int:%vreg0
80 %vreg12<def> = COPY %vreg11<kill>; int:%vreg12 int:%vreg11
96 %vreg15<def> = COPY %vreg8; int:%vreg15 int:%vreg8
112 jump@L <BB#2>
128 
144 %vreg6<def> = PHI %vreg3, <BB#3>, %vreg0, <BB#2>; int:%vreg6,%vreg3,%vreg0
160 %vreg7<earlyclobber,def> = not@II %vreg6; int:%vreg7,%vreg6
176 %vreg9<earlyclobber,def> = ne@III %vreg7<kill>, %vreg8; int:%vreg9,%vreg7 int:%vreg8
192 %vreg14<def> = COPY %vreg13; int:%vreg14 int:%vreg13
208 break@ILL %vreg9<kill>, <BB#2>, <BB#4>; int:%vreg9
224 
240 %vreg1<def> = PHI %vreg12, <BB#0>, %vreg14, <BB#1>; int:%vreg1,%vreg12,%vreg14
256 %vreg2<def> = PHI %vreg15, <BB#0>, %vreg6, <BB#1>; int:%vreg2,%vreg15,%vreg6
272 loop@L <BB#4>
288 br@ILL %vreg1<kill>, <BB#3>, <BB#1>; int:%vreg1
304 
320 %vreg3<def> = COPY %vreg2<kill>; int:%vreg3,%vreg2
336 %vreg3<earlyclobber,def>, %vreg4<earlyclobber,def,dead>, %vreg5<earlyclobber,def,dead> = nextsample@IFF %vreg3; int:%vreg3 float:%vreg4,%vreg5
352 jump@L <BB#1>
368 
384 %vI253<def> = COPY %vreg6<kill>; int:%vreg6
400 return %vI253<imp-use,kill>
416 
BB#0	[0L;128L)
BB#1	[128L;224L)
BB#2	[224L;304L)
BB#3	[304L;368L)
BB#4	[368L;416L)
********** COMPUTING LIVE INTERVALS **********
********** Function: test
BB#0:		# derived from body.lr.ph
		livein register: %vI254 live through +[0L,128L:0)
		livein register: %vI253 live through +[0L,128L:0)
		livein register: %cuI0 killed +[0L,48d:0)
		livein register: %cuI1 killed +[0L,32d:0)
		livein register: %cuI2 killed +[0L,16d:0)
16L	%vreg13<def> = COPY %cuI2<kill>; int:%vreg13
		register: %vreg13 +[16d,128L:0) +[128L,224L:0) +[224L,304L:0) +[304L,368L:0)
32L	%vreg11<def> = COPY %cuI1<kill>; int:%vreg11
		register: %vreg11 +[32d,80d:0)
48L	%vreg8<def> = COPY %cuI0<kill>; int:%vreg8
		register: %vreg8 +[48d,128L:0) +[128L,224L:0) +[224L,304L:0) +[304L,368L:0)
64L	%vreg0<def> = COPY %vI254; int:%vreg0
		register: %vreg0 +[64d,128L:0) +[128L,224L:0) +[224L,304L:0) +[304L,368L:0)
80L	%vreg12<def> = COPY %vreg11<kill>; int:%vreg12 int:%vreg11
		register: %vreg12 +[80d,128L:0)
96L	%vreg15<def> = COPY %vreg8; int:%vreg15 int:%vreg8
		register: %vreg15 +[96d,128L:0)
112L	jump@L <BB#2>
BB#1:		# derived from loop.backedge
144L	%vreg6<def> = PHI %vreg3, <BB#3>, %vreg0, <BB#2>; int:%vreg6,%vreg3,%vreg0
		register: %vreg6 +[144d,224L:0) +[368L,384d:0)
160L	%vreg7<earlyclobber,def> = not@II %vreg6; int:%vreg7,%vreg6
		register: %vreg7 +[160u,176d:0)
176L	%vreg9<earlyclobber,def> = ne@III %vreg7<kill>, %vreg8; int:%vreg9,%vreg7 int:%vreg8
		register: %vreg9 +[176u,208d:0)
192L	%vreg14<def> = COPY %vreg13; int:%vreg14 int:%vreg13
		register: %vreg14 +[192d,224L:0)
208L	break@ILL %vreg9<kill>, <BB#2>, <BB#4>; int:%vreg9
BB#2:		# derived from body
240L	%vreg1<def> = PHI %vreg12, <BB#0>, %vreg14, <BB#1>; int:%vreg1,%vreg12,%vreg14
		register: %vreg1 +[240d,288d:0)
256L	%vreg2<def> = PHI %vreg15, <BB#0>, %vreg6, <BB#1>; int:%vreg2,%vreg15,%vreg6
		register: %vreg2 +[256d,304L:0) +[304L,320d:0)
272L	loop@L <BB#4>
288L	br@ILL %vreg1<kill>, <BB#3>, <BB#1>; int:%vreg1
BB#3:		# derived from false
320L	%vreg3<def> = COPY %vreg2<kill>; int:%vreg3,%vreg2
		register: %vreg3 +[320d,368L:0)
336L	%vreg3<earlyclobber,def>, %vreg4<earlyclobber,def,dead>, %vreg5<earlyclobber,def,dead> = nextsample@IFF %vreg3; int:%vreg3 float:%vreg4,%vreg5
		register: %vreg5 +[336u,336S:0)
		register: %vreg4 +[336u,336S:0)
		register: %vreg3 replace range with [320d,336u:1) RESULT: %vreg3 = [320d,336u:1)[336u,368L:0)  0@336u 1@320d
352L	jump@L <BB#1>
BB#4:		# derived from endloop
384L	%vI253<def> = COPY %vreg6<kill>; int:%vreg6
		register: %vI253 killed +[384d,400d:1)
400L	return %vI253<imp-use,kill>
********** INTERVALS **********
%cuI2,inf = [0L,16d:0)  0@0L-phidef
%vreg0 = [64d,368L:0)  0@64d
%vreg7 = [160u,176d:0)  0@160u
%vreg14 = [192d,224L:0)  0@192d
%vreg2 = [256d,320d:0)  0@256d
%vI254,inf = [0L,128L:0)  0@0L-phidef
%vreg9 = [176u,208d:0)  0@176u
%vreg4 = [336u,336S:0)  0@336u
%vreg11 = [32d,80d:0)  0@32d
%cuI1,inf = [0L,32d:0)  0@0L-phidef
%vreg6 = [144d,224L:0)[368L,384d:0)  0@144d
%vreg13 = [16d,368L:0)  0@16d
%vreg1 = [240d,288d:0)  0@240d
%vI253,inf = [0L,128L:0)[384d,400d:1)  0@0L-phidef 1@384d
%vreg8 = [48d,368L:0)  0@48d
%vreg15 = [96d,128L:0)  0@96d
%vreg3 = [320d,336u:1)[336u,368L:0)  0@336u 1@320d
%cuI0,inf = [0L,48d:0)  0@0L-phidef
%vreg5 = [336u,336S:0)  0@336u
%vreg12 = [80d,128L:0)  0@80d
********** MACHINEINSTRS **********
# Machine code for function test:
Function Live Ins: %vI254, %vI253, %cuI0 in %vreg8, %cuI1 in %vreg11, %cuI2 in %vreg13
Function Live Outs: %vI253

0L	BB#0: derived from LLVM BB %body.lr.ph
	    Live Ins: %vI254 %vI253 %cuI0 %cuI1 %cuI2
16L		%vreg13<def> = COPY %cuI2<kill>; int:%vreg13
32L		%vreg11<def> = COPY %cuI1<kill>; int:%vreg11
48L		%vreg8<def> = COPY %cuI0<kill>; int:%vreg8
64L		%vreg0<def> = COPY %vI254; int:%vreg0
80L		%vreg12<def> = COPY %vreg11<kill>; int:%vreg12 int:%vreg11
96L		%vreg15<def> = COPY %vreg8; int:%vreg15 int:%vreg8
112L		jump@L <BB#2>
	    Successors according to CFG: BB#2

128L	BB#1: derived from LLVM BB %loop.backedge
	    Predecessors according to CFG: BB#2 BB#3
144L		%vreg6<def> = PHI %vreg3, <BB#3>, %vreg0, <BB#2>; int:%vreg6,%vreg3,%vreg0
160L		%vreg7<earlyclobber,def> = not@II %vreg6; int:%vreg7,%vreg6
176L		%vreg9<earlyclobber,def> = ne@III %vreg7<kill>, %vreg8; int:%vreg9,%vreg7 int:%vreg8
192L		%vreg14<def> = COPY %vreg13; int:%vreg14 int:%vreg13
208L		break@ILL %vreg9<kill>, <BB#2>, <BB#4>; int:%vreg9
	    Successors according to CFG: BB#2 BB#4

224L	BB#2: derived from LLVM BB %body
	    Predecessors according to CFG: BB#0 BB#1
240L		%vreg1<def> = PHI %vreg12, <BB#0>, %vreg14, <BB#1>; int:%vreg1,%vreg12,%vreg14
256L		%vreg2<def> = PHI %vreg15, <BB#0>, %vreg6, <BB#1>; int:%vreg2,%vreg15,%vreg6
272L		loop@L <BB#4>
288L		br@ILL %vreg1<kill>, <BB#3>, <BB#1>; int:%vreg1
	    Successors according to CFG: BB#3 BB#1

304L	BB#3: derived from LLVM BB %false
	    Predecessors according to CFG: BB#2
320L		%vreg3<def> = COPY %vreg2<kill>; int:%vreg3,%vreg2
336L		%vreg3<earlyclobber,def>, %vreg4<earlyclobber,def,dead>, %vreg5<earlyclobber,def,dead> = nextsample@IFF %vreg3; int:%vreg3 float:%vreg4,%vreg5
352L		jump@L <BB#1>
	    Successors according to CFG: BB#1

368L	BB#4: derived from LLVM BB %endloop
	    Predecessors according to CFG: BB#1
384L		%vI253<def> = COPY %vreg6<kill>; int:%vreg6
400L		return %vI253<imp-use,kill>

# End machine code for function test.


*** Renumbering SlotIndexes ***
********** COMPUTING LIVE DEBUG VARIABLES: test **********
********** DEBUG VARIABLES **********
********** SIMPLE REGISTER COALESCING **********
********** Function: test
********** JOINING INTERVALS ***********
loop.backedge:
208L	%vreg12<def> = COPY %vreg13; int:%vreg12 int:%vreg13
	Not coalescable.
body:
288L	%vreg2<def> = COPY %vreg3<kill>; int:%vreg2,%vreg3
	Considering merging %vreg3 with %vreg2
		RHS = %vreg2 = [288d,368d:0)  0@288d
		LHS = %vreg3 = [112d,144L:4)[144L,240L:2)[240L,288d:5)[320d,352L:3)[368d,384u:1)[384u,416L:0)[416L,432d:2)  0@384u-phikill 1@368d 2@144L-phidef-phikill 3@320d-phikill 4@112d-phikill 5@240L-phidef
	Interference!
320L	%vreg3<def> = COPY %vreg0; int:%vreg3,%vreg0
	Considering merging %vreg0 with %vreg3
		RHS = %vreg0 = [64d,416L:0)  0@64d
		LHS = %vreg3 = [112d,144L:4)[144L,240L:2)[240L,288d:5)[320d,352L:3)[368d,384u:1)[384u,416L:0)[416L,432d:2)  0@384u-phikill 1@368d 2@144L-phidef-phikill 3@320d-phikill 4@112d-phikill 5@240L-phidef
vexort: RegisterCoalescer.cpp:1388: bool RegistersDefinedFromSameValue(llvm::LiveIntervals&, const llvm::TargetRegisterInfo&, llvm::CoalescerPair&, llvm::VNInfo*, llvm::LiveRange*, llvm::SmallVector<llvm::MachineInstr*, 8u>&): Assertion `Dst == A' failed.
Stack dump:
0.	Running pass 'Simple Register Coalescing' on function '@test'
