Running slice:
core_v7A+vfpneon_vfpv3_neonv1
feature_ARM
0xe0000000 - 0xefffffff (provided (val & 0xf0000000) == 0xe0000000)
encode_decode

FAILED[1110 0110 1000 0000 0000 0000 1011 0000, 0xe68000b0]: Member differs: 'majorOpcode' (SEL      r0,r0,r0 ; ?  )[hit 61440 times] [[bug 1] - unpredictable SEL as STR]
FAILED[1110 0110 1000 0000 0000 0001 0111 0000, 0xe6800170]: Member differs: 'majorOpcode' (SXTAB16  r0,r0,r0 ; ?  )[hit 49152 times] [[bug 2] - unpredictable SXTAB16 to STR]
FAILED[1110 0110 1100 0000 0000 0001 0111 0000, 0xe6c00170]: Member differs: 'majorOpcode' (UXTAB16  r0,r0,r0 ; ?  )[hit 49152 times] [[bug 3] - unpredictable UXTAB16 to STRB]
FAILED[1110 0111 1100 0000 0000 0000 1001 0000, 0xe7c00090]: Member differs: 'bitfieldLsb' (BFI      r0,r0,#1,#32 ; ?  )[hit 126976 times] [[bug 4] - BFI with unpredictable lsb and width combination]
FAILED[1110 1100 1000 0000 0000 1011 0000 0011, 0xec800b03]: Member differs: 'minorOpcode' (FSTMIAX  r0,{d0})[hit 50688 times] [[bug 5] - non-UAL FLSTMX/FLDMX decode as VSTM/VLDM instructions]

288376492 bitpatterns tested, 235184481 passed, 337408 failed, 52854603 skipped (0.12% failure rate)

Failure breakdown:
Not assembled: 0
Not disassembled: 0
Should be unpredictable: 49071465 (17.02%)
Should be undefined: 3642129 (1.26%)
Should not be unpredictable: 9408 (0.00%)
Should not be undefined: 131601 (0.05%)
Member differs: 337408 (0.12%)
Other: 0

[bug 1] echo 0xb0 0x00 0x80 0xe6 | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble

This bitpattern should decode to an unpredictable SEL r0, r0, r0. MC is
decoding this to an STR r0, [r0], r0, lsr #1 which it is incorrectly diagnosing 
as unpredictable.

[bug 2] echo 0x70 0x01 0x80 0xe6 | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble

This bitpattern should decode to an unpredictable SXTAB16 r0, r0, r0. MC is
decoding this to an STR r0, [r0], r0, ror #2 which it is incorrectly diagnosing 
as unpredictable.

[bug 3] echo 0x70 0x01 0xc0 0xe6 | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble

This bitpattern should decode to an unpredictable UXTAB16 r0, r0, r0. MC is
decoding this to an STRB r0, [r0], r0, ror #2 which it is incorrectly diagnosing 
as unpredictable.

[bug 4] echo 0x90 0x00 0xc0 0xe7 | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble
        echo 0x90 0x01 0xc0 0xe7 | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble

This bitpattern decodes to a BFI with an invalid mask operand, which is 
unpredictable. The first example fails with an abort when they are turned on, 
and otherwise creates the instruction BFI r0, r0, #32, #-32.

The second example does not abort and decodes to BFI r0, r0, #1, #2 (0xe7c20090). 

The ARMARM could be clearer on this point, but the real UAL should be

BFI r0, r0, #lsbit #(msbit+1-lsbit) or BFI r0, r0, #3, #-2

In my opinion, the root cause of the problem is that BFI MCInsts store the
mask as a 32-bit operand and converts to and from the msbit and lsbit fields
during encode, decode, assemble and disassemble. I think it should store the 
msbit and lsbit fields as operands and compute the mask at the instruction 
selection phase.

[bug 5] echo 0x03 0x0b 0x80 0xec | ./llvm-mc -triple armv7 --show-inst --show-encoding --disassemble

The bitpattern is decoding as VSTMIA r0, {d0} when it should decode to FSTMIAX r0, {d0}

These instructions are a bit of a curiosity in that they are pre-ARMv6 (VFPv1) 
instruction mnemonics which were not superseded by UAL-style V* mnemonics. They 
still exist in VFPv4 but their use is deprecated. Any VSTM's with odd numbered 
imm8 fields (bottom 8 bits) are the old-style F* encodings, and the encoding i
for the immediate is different.