<div class="gmail_extra">Hello.</div>
<div class="gmail_extra"> </div>
<div class="gmail_extra">I have played with DataLayout and found a solution with is uknown to me.</div>
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<div class="gmail_extra">I added S16 and also s0:16:16, but it had not worked.</div>
<div class="gmail_extra">Then I found that in Z80FrameLowering.h I am calling TargetFrameLowering with stack aligment set to 8. So I changed it to 2 bytes. But this also didn't help.</div>
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<div class="gmail_extra">Then I changed llc to show TargetDataLayout and found that a option is set to a0:0:64.</div>
<div class="gmail_extra">So I changed my Z80DataLayout to a0:0:16. And voila, it started to work and ADD was not longer replaced by OR. Only for add+1 to or, which is correct.</div>
<div class="gmail_extra"> </div>
<div class="gmail_extra">So now I don't understand that a option in datalyout.</div>
<div class="gmail_extra">According doc it is alignment for aggregate type.</div>
<div class="gmail_extra"> </div>
<div class="gmail_extra">But anyhow thanks for help and pointing me in right direction.</div>
<div class="gmail_extra"> </div>
<div class="gmail_extra">Peter.<br> </div>
<div class="gmail_quote">On Wed, Apr 25, 2012 at 4:31 PM, Fan Dawei <span dir="ltr"><<a href="mailto:fandawei.s@gmail.com" target="_blank">fandawei.s@gmail.com</a>></span> wrote:<br>
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<div class="gmail_extra">Hi Peter,</div>
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<div class="gmail_extra">I think the problem is that you did not explicitly define stack alignment in Z80TargetMachine.cpp </div>
<div class="gmail_extra"><br></div>
<div class="gmail_extra">DataLayout("e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8")</div>
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<div class="gmail_extra">Try to add S16 to the string if your stack is 2-byte aligned. Refer to <a style="COLOR:rgb(17,85,204)" href="http://llvm.org/docs/LangRef.html#datalayout" target="_blank">http://llvm.org/docs/LangRef.html#datalayout</a> .</div>
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<div class="gmail_extra">If it does not work, try to specify the layout in the input module using target layout directive.</div>
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<div class="gmail_extra">David</div><br></div>
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<div>On Wed, Apr 25, 2012 at 4:57 PM, Peter Hanzel <span dir="ltr"><<a href="mailto:hanzelpeter@gmail.com" target="_blank">hanzelpeter@gmail.com</a>></span> wrote:<br></div>
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<div>Hello.<br><br>I am playing with LLVM and trying to make Z80 (Zilog Z80) backend.<br>The source code is attached.<br><br>I have succesfully made some simple test. But now I have problem with ADD instruction.<br>The source C code is:<br>
<br>typedef struct<br>{<br>unsigned char id1;<br>unsigned char id2;<br>unsigned char id3;<br><br>} testS;<br><br>void simple()<br>{<br>testS test;<br>test.id1 = 0x40;<br>test.id2 = 0x80;<br>test.id3 = 0xc0;<br>}<br><br>It produces this LLVM IR:<br>
<br>%struct.testS = type { i8, i8, i8 }<br><br>define void @simple() nounwind {<br>entry:<br> %test = alloca %struct.testS, align 1<br> %id1 = getelementptr inbounds %struct.testS* %test, i32 0, i32 0<br> store i8 64, i8* %id1, align 1<br>
%id2 = getelementptr inbounds %struct.testS* %test, i32 0, i32 1<br> store i8 -128, i8* %id2, align 1<br> %id3 = getelementptr inbounds %struct.testS* %test, i32 0, i32 2<br> store i8 -64, i8* %id3, align 1<br> ret void<br>
}<br><br>And with llc -filetype=asm -march=z80 a get this .s file:<br><br>.file "simple4.bc"<br>.text<br>.globl simple<br>.type simple,@function<br>simple: # @simple<br># BB#0: # %entry<br>
ld HL, 8<br>add HL,SP <--- problem line<br>ld DE, 1<br>ld BC, 2<br>ld (SP+6), BC<br>ld B, H<br>ld C, L<br>or BC, DE<br>ld (SP+4), BC<br>ld (HL),64<br>ld D, H<br>ld E, L<br>ld BC, (SP+6)<br>or DE, BC<br>
ld BC, (SP+4)<br>ld H, B<br>ld L, C<br>ld (HL),-128<br>ld H, D<br>ld L, E<br>ld (HL),-64<br>$tmp0:<br>.size simple, ($tmp0)-simple<br><br><br>The problem is that llc replaces ADD instruction with OR.<br><br>Without defining OR16 function, the .S is not generated and claims that it cannot select OR instruction.<br>
So I added OR16 (that's the or BC,DE piece of code).<br><br>But problem is that I am using the first two lines:<br><br>ld HL, 8<br>add HL,SP<br><br>For FrameIndex and the HL register will contain SP which is only two 2bytes aligned.<br>
So "OR with 1" will work, but for second assigned :OR with 2" will not work.<br><br>I suspect that llc is assuming that HL will contain 8 (that's the start) and or-ing 8 with 1 or with 2 is ok.<br>But my HL has also added SP to it.<br>
This is how my ISD::FrameIndex instruction look like:<br><br>def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),<br>"ld $dst, $disp\n\tadd $dst,$src",<br>[(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;<br>
<br>So it say that HL16:$dst wich is only HL register, will be changed.<br>I also tried to change it to<br><(outs HL16:$dst), (ins i16imm:$disp, SP16:$src),<br><br>But the output is the same.<br><br>Can someone tell me what I am doing wrong?<span><font color="#888888"><br>
<br>Peter.<br><br><br><br><br><br><br><br><br></font></span><br></div></div>
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