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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Thanks for the tip, didn't think to look at the AND node as a culprit because we have a similar pattern on a different internal backend and its matching fine.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Micah<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Owen Anderson [mailto:resistor@mac.com]
<br>
<b>Sent:</b> Thursday, April 19, 2012 4:31 PM<br>
<b>To:</b> Villmow, Micah<br>
<b>Cc:</b> LLVM Developers Mailing List<br>
<b>Subject:</b> Re: [LLVMdev] Tablegen to match a literal in an instruction<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes
when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version. Fortunately, the debug output from llc will contain a complete trace of what happened, so you just need to
line it up with GenDAGISel.inc and determine which step did the wrong thing.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">At a guess, I'd say you probably have a type declared wrong somewhere.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">--Owen<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Apr 19, 2012, at 4:05 PM, "Villmow, Micah" <<a href="mailto:Micah.Villmow@amd.com">Micah.Villmow@amd.com</a>> wrote:<o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I'm not at the machine that has the changes, but it was failing at index 0.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Micah</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Owen
Anderson [mailto:resistor@<a href="http://mac.com">mac.com</a>]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Thursday, April 19, 2012 3:35 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Villmow, Micah<br>
<b>Cc:</b><span class="apple-converted-space"> </span>LLVM Developers Mailing List<br>
<b>Subject:</b><span class="apple-converted-space"> </span>Re: [LLVMdev] Tablegen to match a literal in an instruction</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Micah,<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your
and-with-immediate?<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">-Owen<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <<a href="mailto:Micah.Villmow@amd.com"><span style="color:purple">Micah.Villmow@amd.com</span></a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><br>
<br>
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<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">What I am trying to do is take a register/register pattern and change it to a register/immediate.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">So for example, I have this pattern:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern></span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">: Instruction {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let Namespace = "AMDIL";</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> dag OutOperandList = outs;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> dag InOperandList = ins;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> ILOpCode operation = op;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let Pattern = pattern;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let AsmString = !strconcat(asmstr, "\n");</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> bit hasIEEEFlag = 0;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> bit hasZeroOpFlag = 0;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> RegisterClass sReg0, RegisterClass sReg1></span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> !strconcat(op.Text, " $dst, $src0, $src1"),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">defm AND : BinaryOpMCInt<IL_OP_AND, and>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I want to turn this into a register/immediate pattern by changing it to:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern></span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">: Instruction {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let Namespace = "AMDIL";</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> dag OutOperandList = outs;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> dag InOperandList = ins;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let Pattern = pattern;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> let AsmString = !strconcat(asmstr, "\n");</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">multiclass BinaryOp<SDNode OpNode, RegisterClass dReg,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> RegisterClass sReg0, RegisterClass sReg1, Operand lit></span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">{</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> !strconcat(op.Text, " $dst, $src0, $src1"),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> "and $dst, $src0, $src1"),</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> [(set dReg:$dst, (OpNode sReg0:$src0, imm:$src1))]>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">multiclass BinaryOpMCInt<SDNode OpNode> {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> defm _i32 : BinaryOp<OpNode, GPRI32, GPRI32, GPRI32, i32imm>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">defm AND : BinaryOpMCInt<and>;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">When I run on a simple program which just ands a value and writes to memory, I get this error:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">LLVM ERROR: Cannot select: 0x99555d0: i32 = Constant<2> [ORD=7] [ID=8]</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Where 0x99555d0 is only used as the second operand of the 'and' node.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">So, how can I figure out what I'm doing wrong? Does anyone see anything majorly wrong here?</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Thanks,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Micah</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:13.5pt;font-family:"Helvetica","sans-serif"">_______________________________________________<br>
LLVM Developers mailing list<br>
<a href="mailto:LLVMdev@cs.uiuc.edu"><span style="color:purple">LLVMdev@cs.uiuc.edu</span></a><span class="apple-converted-space"> </span> <a href="http://llvm.cs.uiuc.edu"><span style="color:purple">http://llvm.cs.uiuc.edu</span></a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev"><span style="color:purple">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</span></a></span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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