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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">I'm trying to build a standalone assembler for Mips using AsmParser.<br>
<br>
Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation.<br>
<br>
I am getting an assertion for what I believe are multiple register definitions with the same name.<br>
<br>
llvm-tblgen: /home/jcarter/workarea/asm/llvm/utils/TableGen/StringMatcher.cpp:52: bool llvm::StringMatcher::EmitStringMatcherForChar(const std::vector<const std::pair<std::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::basic_string<char,
std::char_traits<char>, std::allocator<char> > >*, std::allocator<const std::pair<std::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::basic_string<char, std::char_traits<char>, std::allocator<char> > >*> >&, unsigned int, unsigned
int) const: Assertion `Matches.size() == 1 && "Had duplicate keys to match on"' failed.<br>
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*********************************<br>
Background for Mips register sets:<br>
*********************************<br>
<br>
The Mips architecture has register names that are context sensitive. <br>
<br>
For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance.<br>
<br>
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;<br>
def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;<br>
<br>
It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double point precision. All of which share the same register name.<br>
<br>
/// Mips Single point precision FPU Registers<br>
def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;<br>
<br>
/// Mips Double point precision FPU Registers (aliased<br>
/// with the single precision to hold 64 bit values)<br>
def D0 : AFPR< 0, "F0", [F0, F1]>;<br>
<br>
/// Mips Double point precision FPU Registers in MFP64 mode.<br>
def D0_64 : AFPR64<0, "F0", [F0]>;<br>
<br>
Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.<br>
<br>
The examples here are from lib/Target/Mips/MipsRegisterInfo.td.<br>
<br>
Do I just need to use/write another register parser? Or is there a clever way of defining the context sensitive Mips register set?<br>
<br>
Thanks,<br>
<br>
Jack<br>
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