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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp.
<br>
<br>
What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher?<br>
<br>
<br>
For the Mips platform we create the following .inc files through tblgen.<br>
<br>
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)<br>
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)<br>
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)<br>
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)<br>
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)<br>
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)<br>
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)<br>
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)<br>
add_public_tablegen_target(MipsCommonTableGen)<br>
<br>
When I started trying to generate MipsGenAsmMatcher.inc for the assembler I started getting errors.<br>
<br>
tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.tdIncluded from Mips.td:24:<br>
MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens<br>
defm LWL : LoadUnAlign32<0x22>;<br>
<br>
How does it get a token?<br>
<br>
Commenting out this code I got farther and found that a register that didn't have a formal def in MipsRegisterInfo.td would get flagged.<br>
<br>
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),<br>
<br>
% tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td<br>
Included from Mips.td:24:<br>
Included from MipsInstrInfo.td:1120:<br>
Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'<br>
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;<br>
^<br>
<br>
Any information on this would be great.<br>
<br>
Cheers,<br>
<br>
Jack<br>
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