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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I’ve been thinking about ways to get around this in the short term for some time, <o:p></o:p></p><p class=MsoNormal><a href="http://llvm.org/bugs/show_bug.cgi?id=1388">http://llvm.org/bugs/show_bug.cgi?id=1388</a><o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>An end-user workaround is possibly to use at least one register > r7 for the MOV form of the instruction. <o:p></o:p></p><p class=MsoNormal>In that case, what is listed in the bug as the CPY instruction (which is the ARMv6 version generated if both Rd and Rm are <= r7) will <o:p></o:p></p><p class=MsoNormal>become a valid MOV instruction all the way down to ARMv4T. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Even if flags aren’t modeled correctly on ARM yet, it seems like this instruction could be forced to a high register safely, <o:p></o:p></p><p class=MsoNormal>but unfortunately I don’t understand the target code enough yet to implement this. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The other (ugly and slow) option might be to encode the low-register versions with a PUSH Rm / POP Rd pair when<o:p></o:p></p><p class=MsoNormal>on ARMv5 or less. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Any thoughts?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>-Gordon Keiser<o:p></o:p></p><p class=MsoNormal>Software Development Engineer<o:p></o:p></p><p class=MsoNormal>Arxan Technologies, Inc.<o:p></o:p></p><p class=MsoNormal>1305 Cumberland Ave, Ste 215<o:p></o:p></p><p class=MsoNormal>West Lafayette, IN <o:p></o:p></p><p class=MsoNormal>47906<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p></div></body></html>