<html><body><div style="color:#000; background-color:#fff; font-family:times new roman, new york, times, serif;font-size:12pt"><div style="font-family: 'times new roman', 'new york', times, serif; font-size: 12pt; "><span><br></span></div><div style="font-family: 'times new roman', 'new york', times, serif; font-size: 12pt; ">Hello Jim.</div><div><span style="font-size: 12pt;">Just out of </span><span style="font-size: 16px;">curiosity, won't such mechanism work via the patterns from instructions defs?</span></div><div><span style="font-size: 16px;"><br></span></div><div><span style="font-size: 16px;">Thanks.</span></div><div><span style="font-size: 16px;">Girish.</span></div><div style="font-family: 'times new roman', 'new york', times, serif; font-size: 12pt; "><br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; margin-top: 5px; padding-left: 5px;"> <div style="font-size: 12pt; font-family: 'times new roman', 'new
york', times, serif; "> <div style="font-size: 12pt; font-family: 'times new roman', 'new york', times, serif; "> <font size="2" face="Arial"> <hr size="1"> <b><span style="font-weight:bold;">From:</span></b> Jim Grosbach <grosbach@apple.com><br> <b><span style="font-weight: bold;">To:</span></b> Johannes Birgmeier <e0902998@student.tuwien.ac.at> <br><b><span style="font-weight: bold;">Cc:</span></b> LLVM Developers Mailing List <llvmdev@cs.uiuc.edu> <br> <b><span style="font-weight: bold;">Sent:</span></b> Monday, 19 December 2011 10:33 PM<br> <b><span style="font-weight: bold;">Subject:</span></b> Re: [LLVMdev] Stop MachineCSE on certain instructions<br> </font> <br>Hi Johannes,<br><br>You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions
together.<br><br>-Jim<br><br>On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote:<br><br>> Hello,<br>> <br>> I'm writing for a backend and have a complicated instruction bundle (3 <br>> instructions) that has to be executed like a single block (meaning: if <br>> the first instruction is executed, all three have to be executed to <br>> obtain the result, though not necessarily without other instructions in <br>> between). Unfortunately, MachineCSE gets in the way sometimes and rips <br>> it apart.<br>> <br>> Is there a way to stop CSE from doing its thing (common subexpression <br>> elimination) for certain instructions?<br>> <br>> I've already tried glueing (gluing?) them together, but that doesn't <br>> seem to make a difference.<br>> <br>> Regards,<br>> Johannes Birgmeier<br>> _______________________________________________<br>> LLVM Developers mailing list<br>> <a
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