<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div>On Dec 5, 2011, at 7:42 PM, Dan Gohman wrote:</div><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; ">For example, suppose we want to convert the && to &, and the ?: to a<br>select, in this code:<br><br>if (a && (b ? (c + d) : e)) {<br><br>because we have a CPU architecture with poor branch prediction, or<br>because we want more ILP, or because of some other reason. Here's what the<br>LLVM IR for that might look like:<br><br> %t0 = add nsw i32 %c, %d<br> %t1 = select i1 %b, i32 %t0, i32 %e<br> %t2 = icmp ne i32 %t1, 0<br> %t3 = and i1 %a, %t2<br> br i1 %t3, ...<br><br>The extra branching is gone, yay. But now we've put an add nsw out there<br>to be executed unconditionally. If we make the select an observation<br>point, we'd have introduced undefined behavior on a path that didn't<br>previously have it.<br><br>A foodtaster instruction doesn't really solve this problem, because<br>we'd have to put it between the add and the select, and it would be<br>just as problematic.<br><br>The current definition of nsw is an attempt to avoid arbitrary<br>limitations and keep the system as flexible as possible.<br><br>One could argue that aggressive speculation is a low-level optimization<br>better suited to CodeGen than the optimizer, as LLVM divides them, and<br>that perhaps the cost for providing this level of flexibility in the<br>optimizer is too high, but that's a different argument.</span></blockquote></div><br><div><div>The optimizations we're talking about are forms of safe</div><div>speculation. Doing that at IR level is fine.</div><div><br></div><div>Hardware support for NaT bits + check instructions have been popping</div><div>up on this message thread. Hardware speculation exists solely to</div><div>support unsafe speculation, in which certain operations need to be</div><div>reexecuted under certain conditions. It is not something we would ever</div><div>want to represent in IR. It isn't ammenable to CFG+SSA form.</div><div><br></div><div>Runtime checking for undefined behavior would be implemented as</div><div>overflow checks, etc. by the front end. I don't think it's related to</div><div>unsafe speculation. In other words, I don't see the purpose of a</div><div>"check/foodtaster" instruction.</div></div><div><br></div><div>-Andy</div></body></html>