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<p class=MsoNormal><span style='color:#1F497D'>Hi Micah,<o:p></o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'>I’m no core developer, but
FWIW here are my thoughts:<o:p></o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'>I’m general I think the
patch is too OpenCL oriented, and I have some niggling qualms about other parts.
Specifically (comments inline):<o:p></o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p>
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<p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:
"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;
font-family:"Tahoma","sans-serif"'> llvmdev-bounces@cs.uiuc.edu
[mailto:llvmdev-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Villmow, Micah<br>
<b>Sent:</b> 03 October 2011 19:37<br>
<b>To:</b> llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> [LLVMdev] [RFC] Proposal to make LLVM-IR endian agnostic<o:p></o:p></span></p>
</div>
</div>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal><span lang=EN-US>One of the projects I am working on with
others is to make LLVM-IR endian agnostic. <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>So, I am sending out this proposal for
feedback to the LLVM community. I’ve attached<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>pretty version of the proposal in PDF
format and pasted a 80-column safe text version<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>below. <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>I’m looking forward to comments and
feedback.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>PROBLEM QUESTION:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>How does a vendor simplify the compiler
stack across multiple target devices<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>by removing endianess from the IR
representation?<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>This is not the
question that your RFC answers. Your RFC answers a superset of just “represent
endianness”.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>DEFINITIONS:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Global Memory - Memory that is visible to
all threads in a process/program, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>e.g. video ram. This includes all
read-only, write-only and read-write memories<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>on the system that are visible to all
threads.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>What has this got to
do with endianness?<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>INTRINSICS:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>This proposal introduces new sets of
intrinsics, two load intrinsics and two <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>store intrinsics. The sets are as follows:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>declare <type>
@llvm.portable.load.e.<type>(<type>* ptr, , i32 alignment, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i1 host, i1 atomic, i1 volatile, i1
nontemporal, i1 singlethread) <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>// little endian load<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>declare <type>
@llvm.portable.load.E.<type>(<type>* ptr, i32 alignment, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i1 host, i1 atomic, i1 volatile, i1
nontemporal, i1 singlethread) <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>// big endian load<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>declare void
@llvm.portable.store.e.<type>(<type> data, <type>* ptr, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i32 alignment, i1 host, i1 atomic, i1
volatilei1 nontemporal, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i1 singlethread) // little endian store<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>declare void
@llvm.portable.store.E.<type>(<type> data, <type>* ptr, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i32 alignment, i1 host, i1 atomic, i1
volatile, i1 nontemporal, <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>i1 singlethread) // big endian store<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span
lang=EN-US style='font-family:Symbol;color:#1F497D'><span style='mso-list:Ignore'>·<span
style='font:7.0pt "Times New Roman"'>
</span></span></span><![endif]><span lang=EN-US style='color:#1F497D'>I don’t
like the ‘e’/’E’ representation. If there were only little
or big endian loads throughout an IR file, it wouldn’t be obvious to me
what the ‘e’/’E’ meant. It’s only seeing the two
in tandem where it jumps out at me. I’d prefer the standard ‘le’/’be’.<o:p></o:p></span></p>
<p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span
lang=EN-US style='font-family:Symbol;color:#1F497D'><span style='mso-list:Ignore'>·<span
style='font:7.0pt "Times New Roman"'>
</span></span></span><![endif]><span lang=EN-US style='color:#1F497D'>You’ve
put the OpenCL concept of “host” and “device” in a
supposedly target-agnostic IR. Why should there be only one device? More
importantly, why is host/device an attribute of the load or store as opposed to
the pointer to load/store to? Does it semantically make sense to have both a
host load and a device load of the same memory location in the same module?<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>POINTER ATTRIBUTES:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>-------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>In OpenCL, a pointer can have attributes
attached, and this information needs <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>to be encoded. In LLVM, the method of
encoding extra information is via <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>metadata nodes and this is used so that the
intrinsic do not need to be <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>modified to add extra information. One
example of this is the endian(host) <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>attribute that can be attached to a pointer
argument(see 6.10.3 of OpenCL <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>1.1 spec). This information can be encoded
in a metadata node which is attached<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>to the intrinsic. An example encoding
of this information is as follows:<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>!0 = metadata !{<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US> i32, ;; Tag = <OpenCL version
number> using the official OpenCL version macro<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US> i1,;;Boolean value to specify that
load is from host on true, device on false<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US> metadata ;; List of attributes for
this intrinsic instruction<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>}<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>Does this subsection
add anything extra to the RFC? It talks about a format for metadata, but doesn’t
appear to really add any suggestions or requirements for changing LLVM IR.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>If your intention was
just to make the IR endian-agnostic, I don’t see why you wouldn’t
just propose an extra attribute on the load/store instructions (load be %0,
load le %0) instead of recreating all loads and stores in a new form and having
to make all passes interact with them.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>My general summary is
that I think your suggestions take a “somewhat language-agnostic and
somewhat target-agnostic” IR and turn it into a “somewhat
language-dependent and more target-agnostic” IR, by embedding OpenCL
specifics. I’m not sure I think that’s the best way to go.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>Cheers,<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'>James<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Thanks,<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Micah Villmow<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
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