<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Sep 29, 2011, at 2:19 AM, Heikki Kultala wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Optima; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><span class="Apple-style-span" style="font-family: monospace; ">Our TCE backend (which is not in the official llvm repo) benefits<span class="Apple-converted-space"> </span><br>greatly from information that which memory load/store is a spill<span class="Apple-converted-space"> </span><br>generated by register allocation.<br><br>These spill memory operation can never alias with other memory<span class="Apple-converted-space"> </span><br>operations, and our own instruction scheduler can optimize much better<span class="Apple-converted-space"> </span><br>with better alias information.<br></span></span></blockquote></div><br><div>This information is available from the instruction's memory operands.</div><div><br></div><div>See EmitComments() in lib/CodeGen/AsmPrinter/AsmPrinter.cpp.</div><div><br></div><div>/jakob</div><div><br></div></body></html>