<html><body><div style="color:#000; background-color:#fff; font-family:arial, helvetica, sans-serif;font-size:12pt"><div><span><br></span></div><div><span>Thank you for the answers, Jakob! That's really informative for someone who is still new to LLVM like me. Please see my responses below.</span></div><div><span><br></span></div><div><span>-Ghassan <br></span></div><div><br></div><div style="font-family: arial,helvetica,sans-serif; font-size: 12pt;"><div style="font-family: times new roman,new york,times,serif; font-size: 12pt;"><font face="Arial" size="2"><hr size="1"><b><span style="font-weight: bold;">From:</span></b> Jakob Stoklund Olesen <stoklund@2pi.dk><br><b><span style="font-weight: bold;">To:</span></b> Ghassan Shobaki <ghassan_shobaki@yahoo.com><br><b><span style="font-weight: bold;">Cc:</span></b> "llvmdev@cs.uiuc.edu" <llvmdev@cs.uiuc.edu><br><b><span style="font-weight: bold;">Sent:</span></b> Tuesday, August 16,
2011 12:52 AM<br><b><span style="font-weight: bold;">Subject:</span></b> Re: [LLVMdev] Register Pressure Computation during Pre-Allocation Scheduling<br></font><br><div id="yiv1595100037"><br><div><div>On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote:</div><br><div>>This information is only computed immediately before register allocation. Passes that run after scheduling can significantly change the register pressure. In<br>> particular MachineCSE and MachineLICM do this.<br><br>Ghassan: I know that phase ordering is a non-trivial problem that does not have a perfect solution (like most compiler optimization problems!), but I wonder why LLVM runs such passes between scheduling and allocation. One would expect a register pressure reduction pass to be placed as close as possible to the register allocation pass. Ideally, you would like to have an integrated algorithm that does allocation and scheduling simultaneously, but such an integrated
solution is usually not implemented due to its complexity. So, my questions are:<br>(1) CSE naturally tends to increase reg pressure. Is there any particular reason for doing CSE between scheduling and allocation instead of doing it, say before scheduling?<br>(2) How easy will it be to change the phase ordering in LLVM without breaking things? Where is the phase ordering done? How do we know if there are dependencies among certain phases?<br>(3) Does LLVM have command-line options for turning off phases like CSE and LICM? <br><br></div><div><br></div><br><div>>These DAG nodes are also used to copy to/from physical registers before and after calls.</div><div>>Virtual registers defined by PHI instructions will also appear as CopyFromReg operands.</div><br>Ghassan: So, is there a way to distinguish the ones that represent live-in and live-out regs?<br>Failing to recognize CopyFromReg and CopyToReg instrs that represent live-in/live-out regs, our
scheduler will treat them as regular instructions and may move some of them to the middle of the block, thus resulting in an incorrect under-estimate of reg pressure. We would like to avoid that if possible. <div><br></div><div>/jakob</div><div><br></div></div></div><br><br></div></div></div></body></html>