Args: llc --march=amdil --mcpu=caicos _temp_0_caicos_optimized.bc -debug -print-after-all 

Features:caicos
CPU:rv770*** IR Dump After Target Data Layout ***; ModuleID = '_temp_0_caicos_optimized.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
target triple = "amdil-pc-amdopencl"

%0 = type { i8*, i8*, i8*, i8*, i32 }
%struct._MonteCalroAttrib = type <{ <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> }>

@sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
@fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
@lvgv = internal constant [0 x i8*] zeroinitializer
@llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void (%struct._MonteCalroAttrib*, i32, i32, <4 x i32> addrspace(1)*, <4 x float> addrspace(1)*, <4 x float> addrspace(1)*)* @__OpenCL_calPriceVega_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"

define void @__OpenCL_calPriceVega_kernel(%struct._MonteCalroAttrib* nocapture byval %attrib, i32 %noOfSum, i32 %width, <4 x i32> addrspace(1)* nocapture %randArray, <4 x float> addrspace(1)* nocapture %priceSamples, <4 x float> addrspace(1)* nocapture %pathDeriv) nounwind {
entry:
  %0 = tail call <4 x i32> @__amdil_get_global_id_int() nounwind
  %1 = extractelement <4 x i32> %0, i32 0
  %2 = tail call <4 x i32> @__amdil_get_global_id_int() nounwind
  %3 = extractelement <4 x i32> %2, i32 1
  %tmp4 = mul i32 %3, %width
  %tmp6 = add i32 %tmp4, %1
  %tmp14 = shl i32 %tmp6, 1
  %arrayidx15 = getelementptr <4 x float> addrspace(1)* %priceSamples, i32 %tmp14
  store <4 x float> zeroinitializer, <4 x float> addrspace(1)* %arrayidx15, align 16
  %tmp241 = or i32 %tmp14, 1
  %arrayidx25 = getelementptr <4 x float> addrspace(1)* %priceSamples, i32 %tmp241
  store <4 x float> zeroinitializer, <4 x float> addrspace(1)* %arrayidx25, align 16
  ret void
}

declare <4 x i32> @__amdil_get_global_id_int() nounwind


# *** IR Dump After AMD IL EG Pointer Manager Pass ***:
# Machine code for function __OpenCL_calPriceVega_kernel:
Function Live Ins: %Rz1 in reg%2147483650, %Rx1000 in reg%2147483652

BB#0: derived from LLVM BB %entry
    Live Ins: %Rz1 %Rx1000
	%vreg4<def> = COPY %Rx1000; GPRI32:%vreg4
	%vreg2<def> = COPY %Rz1; GPRI32:%vreg2
	%vreg6<def> = LOADCONST_f32 0.000000e+00; GPRF32:%vreg6
	%vreg7<def> = VCREATE_v4f32 %vreg6; GPRV4F32:%vreg7 GPRF32:%vreg6
	%vreg8<def> = VINSERT_v4f32 %vreg7<kill>, %vreg6, 197121, 16777216; GPRV4F32:%vreg8,%vreg7 GPRF32:%vreg6
	%vreg9<def> = VINSERT_v4f32 %vreg8<kill>, %vreg6, 67109377, 65536; GPRV4F32:%vreg9,%vreg8 GPRF32:%vreg6
	%vreg10<def> = VINSERT_v4f32 %vreg9<kill>, %vreg6, 67305473, 256; GPRV4F32:%vreg10,%vreg9 GPRF32:%vreg6
	%vreg11<def> = GET_GLOBAL_ID; GPRV4I32:%vreg11
	%vreg12<def> = GET_GLOBAL_ID; GPRV4I32:%vreg12
	%vreg13<def> = VEXTRACT_v4i32 %vreg12<kill>, 2; GPRI32:%vreg13 GPRV4I32:%vreg12
	%vreg14<def> = SMUL_i32 %vreg13<kill>, %vreg2; GPRI32:%vreg14,%vreg13,%vreg2
	%vreg15<def> = VEXTRACT_v4i32 %vreg11<kill>, 1; GPRI32:%vreg15 GPRV4I32:%vreg11
	%vreg16<def> = CUSTOM_ADD_i32 %vreg14<kill>, %vreg15<kill>; GPRI32:%vreg16,%vreg14,%vreg15
	%vreg17<def> = LOADCONST_i32 5; GPRI32:%vreg17
	%vreg18<def> = SHL_i32 %vreg16<kill>, %vreg17<kill>; GPRI32:%vreg18,%vreg16,%vreg17
	%vreg19<def> = CUSTOM_ADD_i32 %vreg4, %vreg18; GPRI32:%vreg19,%vreg4,%vreg18
	GLOBALSTORE_v4f32 %vreg10, %vreg19<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx15] GPRV4F32:%vreg10 GPRI32:%vreg19
	%vreg20<def> = LOADCONST_i32 16; GPRI32:%vreg20
	%vreg21<def> = BINARY_OR_i32 %vreg18, %vreg20<kill>; GPRI32:%vreg21,%vreg18,%vreg20
	%vreg22<def> = CUSTOM_ADD_i32 %vreg4, %vreg21<kill>; GPRI32:%vreg22,%vreg4,%vreg21
	GLOBALSTORE_v4f32 %vreg10, %vreg22<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx25] GPRV4F32:%vreg10 GPRI32:%vreg22
	RETURN

# End machine code for function __OpenCL_calPriceVega_kernel.

Machine Function
********** REWRITING TWO-ADDR INSTRS **********
********** Function: __OpenCL_calPriceVega_kernel
********** PROCESS IMPLICIT DEFS **********
********** Function: __OpenCL_calPriceVega_kernel
0 
16 %vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
32 %vreg2<def> = COPY %Rz1<kill>; GPRI32:%vreg2
48 %vreg6<def> = LOADCONST_f32 0.000000e+00; GPRF32:%vreg6
64 %vreg7<def> = VCREATE_v4f32 %vreg6; GPRV4F32:%vreg7 GPRF32:%vreg6
80 %vreg8<def> = VINSERT_v4f32 %vreg7<kill>, %vreg6, 197121, 16777216; GPRV4F32:%vreg8,%vreg7 GPRF32:%vreg6
96 %vreg9<def> = VINSERT_v4f32 %vreg8<kill>, %vreg6, 67109377, 65536; GPRV4F32:%vreg9,%vreg8 GPRF32:%vreg6
112 %vreg10<def> = VINSERT_v4f32 %vreg9<kill>, %vreg6<kill>, 67305473, 256; GPRV4F32:%vreg10,%vreg9 GPRF32:%vreg6
128 %vreg11<def> = GET_GLOBAL_ID; GPRV4I32:%vreg11
144 %vreg12<def> = GET_GLOBAL_ID; GPRV4I32:%vreg12
160 %vreg13<def> = VEXTRACT_v4i32 %vreg12<kill>, 2; GPRI32:%vreg13 GPRV4I32:%vreg12
176 %vreg14<def> = SMUL_i32 %vreg13<kill>, %vreg2<kill>; GPRI32:%vreg14,%vreg13,%vreg2
192 %vreg15<def> = VEXTRACT_v4i32 %vreg11<kill>, 1; GPRI32:%vreg15 GPRV4I32:%vreg11
208 %vreg16<def> = CUSTOM_ADD_i32 %vreg14<kill>, %vreg15<kill>; GPRI32:%vreg16,%vreg14,%vreg15
224 %vreg17<def> = LOADCONST_i32 5; GPRI32:%vreg17
240 %vreg18<def> = SHL_i32 %vreg16<kill>, %vreg17<kill>; GPRI32:%vreg18,%vreg16,%vreg17
256 %vreg19<def> = CUSTOM_ADD_i32 %vreg4, %vreg18; GPRI32:%vreg19,%vreg4,%vreg18
272 GLOBALSTORE_v4f32 %vreg10, %vreg19<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx15] GPRV4F32:%vreg10 GPRI32:%vreg19
288 %vreg20<def> = LOADCONST_i32 16; GPRI32:%vreg20
304 %vreg21<def> = BINARY_OR_i32 %vreg18<kill>, %vreg20<kill>; GPRI32:%vreg21,%vreg18,%vreg20
320 %vreg22<def> = CUSTOM_ADD_i32 %vreg4<kill>, %vreg21<kill>; GPRI32:%vreg22,%vreg4,%vreg21
336 GLOBALSTORE_v4f32 %vreg10<kill>, %vreg22<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx25] GPRV4F32:%vreg10 GPRI32:%vreg22
352 RETURN
368 
MBB 0 (0x34bfee8) - [0L, 368L]
********** COMPUTING LIVE INTERVALS **********
********** Function: __OpenCL_calPriceVega_kernel
BB#0:		# derived from entry
		livein register: %Rz1 killed +[0L,32d:0)
		livein register: %Rx1000 killed +[0L,16d:0)
16L	%vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
		register: %vreg4 +[16d,320d:0)
32L	%vreg2<def> = COPY %Rz1<kill>; GPRI32:%vreg2
		register: %vreg2 +[32d,176d:0)
48L	%vreg6<def> = LOADCONST_f32 0.000000e+00; GPRF32:%vreg6
		register: %vreg6 +[48d,112d:0)
64L	%vreg7<def> = VCREATE_v4f32 %vreg6; GPRV4F32:%vreg7 GPRF32:%vreg6
		register: %vreg7 +[64d,80d:0)
80L	%vreg8<def> = VINSERT_v4f32 %vreg7<kill>, %vreg6, 197121, 16777216; GPRV4F32:%vreg8,%vreg7 GPRF32:%vreg6
		register: %vreg8 +[80d,96d:0)
96L	%vreg9<def> = VINSERT_v4f32 %vreg8<kill>, %vreg6, 67109377, 65536; GPRV4F32:%vreg9,%vreg8 GPRF32:%vreg6
		register: %vreg9 +[96d,112d:0)
112L	%vreg10<def> = VINSERT_v4f32 %vreg9<kill>, %vreg6<kill>, 67305473, 256; GPRV4F32:%vreg10,%vreg9 GPRF32:%vreg6
		register: %vreg10 +[112d,336d:0)
128L	%vreg11<def> = GET_GLOBAL_ID; GPRV4I32:%vreg11
		register: %vreg11 +[128d,192d:0)
144L	%vreg12<def> = GET_GLOBAL_ID; GPRV4I32:%vreg12
		register: %vreg12 +[144d,160d:0)
160L	%vreg13<def> = VEXTRACT_v4i32 %vreg12<kill>, 2; GPRI32:%vreg13 GPRV4I32:%vreg12
		register: %vreg13 +[160d,176d:0)
176L	%vreg14<def> = SMUL_i32 %vreg13<kill>, %vreg2<kill>; GPRI32:%vreg14,%vreg13,%vreg2
		register: %vreg14 +[176d,208d:0)
192L	%vreg15<def> = VEXTRACT_v4i32 %vreg11<kill>, 1; GPRI32:%vreg15 GPRV4I32:%vreg11
		register: %vreg15 +[192d,208d:0)
208L	%vreg16<def> = CUSTOM_ADD_i32 %vreg14<kill>, %vreg15<kill>; GPRI32:%vreg16,%vreg14,%vreg15
		register: %vreg16 +[208d,240d:0)
224L	%vreg17<def> = LOADCONST_i32 5; GPRI32:%vreg17
		register: %vreg17 +[224d,240d:0)
240L	%vreg18<def> = SHL_i32 %vreg16<kill>, %vreg17<kill>; GPRI32:%vreg18,%vreg16,%vreg17
		register: %vreg18 +[240d,304d:0)
256L	%vreg19<def> = CUSTOM_ADD_i32 %vreg4, %vreg18; GPRI32:%vreg19,%vreg4,%vreg18
		register: %vreg19 +[256d,272d:0)
272L	GLOBALSTORE_v4f32 %vreg10, %vreg19<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx15] GPRV4F32:%vreg10 GPRI32:%vreg19
288L	%vreg20<def> = LOADCONST_i32 16; GPRI32:%vreg20
		register: %vreg20 +[288d,304d:0)
304L	%vreg21<def> = BINARY_OR_i32 %vreg18<kill>, %vreg20<kill>; GPRI32:%vreg21,%vreg18,%vreg20
		register: %vreg21 +[304d,320d:0)
320L	%vreg22<def> = CUSTOM_ADD_i32 %vreg4<kill>, %vreg21<kill>; GPRI32:%vreg22,%vreg4,%vreg21
		register: %vreg22 +[320d,336d:0)
336L	GLOBALSTORE_v4f32 %vreg10<kill>, %vreg22<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx25] GPRV4F32:%vreg10 GPRI32:%vreg22
352L	RETURN
********** INTERVALS **********
%vreg7 = [64d,80d:0)  0@64d
%vreg14 = [176d,208d:0)  0@176d
%vreg21 = [304d,320d:0)  0@304d
%vreg2 = [32d,176d:0)  0@32d
%vreg9 = [96d,112d:0)  0@96d
%Rx1000,1.#INF00e+00 = [0L,16d:0)  0@0L-phidef
%vreg16 = [208d,240d:0)  0@208d
%vreg4 = [16d,320d:0)  0@16d
%vreg11 = [128d,192d:0)  0@128d
%vreg18 = [240d,304d:0)  0@240d
%vreg6 = [48d,112d:0)  0@48d
%vreg13 = [160d,176d:0)  0@160d
%vreg20 = [288d,304d:0)  0@288d
%vreg8 = [80d,96d:0)  0@80d
%vreg15 = [192d,208d:0)  0@192d
%vreg22 = [320d,336d:0)  0@320d
%vreg10 = [112d,336d:0)  0@112d
%vreg17 = [224d,240d:0)  0@224d
%Rz1,1.#INF00e+00 = [0L,32d:0)  0@0L-phidef
%vreg12 = [144d,160d:0)  0@144d
%vreg19 = [256d,272d:0)  0@256d
********** MACHINEINSTRS **********
# Machine code for function __OpenCL_calPriceVega_kernel:
Function Live Ins: %Rz1 in reg%2147483650, %Rx1000 in reg%2147483652

0L	BB#0: derived from LLVM BB %entry
	    Live Ins: %Rz1 %Rx1000
16L		%vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
32L		%vreg2<def> = COPY %Rz1<kill>; GPRI32:%vreg2
48L		%vreg6<def> = LOADCONST_f32 0.000000e+00; GPRF32:%vreg6
64L		%vreg7<def> = VCREATE_v4f32 %vreg6; GPRV4F32:%vreg7 GPRF32:%vreg6
80L		%vreg8<def> = VINSERT_v4f32 %vreg7<kill>, %vreg6, 197121, 16777216; GPRV4F32:%vreg8,%vreg7 GPRF32:%vreg6
96L		%vreg9<def> = VINSERT_v4f32 %vreg8<kill>, %vreg6, 67109377, 65536; GPRV4F32:%vreg9,%vreg8 GPRF32:%vreg6
112L		%vreg10<def> = VINSERT_v4f32 %vreg9<kill>, %vreg6<kill>, 67305473, 256; GPRV4F32:%vreg10,%vreg9 GPRF32:%vreg6
128L		%vreg11<def> = GET_GLOBAL_ID; GPRV4I32:%vreg11
144L		%vreg12<def> = GET_GLOBAL_ID; GPRV4I32:%vreg12
160L		%vreg13<def> = VEXTRACT_v4i32 %vreg12<kill>, 2; GPRI32:%vreg13 GPRV4I32:%vreg12
176L		%vreg14<def> = SMUL_i32 %vreg13<kill>, %vreg2<kill>; GPRI32:%vreg14,%vreg13,%vreg2
192L		%vreg15<def> = VEXTRACT_v4i32 %vreg11<kill>, 1; GPRI32:%vreg15 GPRV4I32:%vreg11
208L		%vreg16<def> = CUSTOM_ADD_i32 %vreg14<kill>, %vreg15<kill>; GPRI32:%vreg16,%vreg14,%vreg15
224L		%vreg17<def> = LOADCONST_i32 5; GPRI32:%vreg17
240L		%vreg18<def> = SHL_i32 %vreg16<kill>, %vreg17<kill>; GPRI32:%vreg18,%vreg16,%vreg17
256L		%vreg19<def> = CUSTOM_ADD_i32 %vreg4, %vreg18; GPRI32:%vreg19,%vreg4,%vreg18
272L		GLOBALSTORE_v4f32 %vreg10, %vreg19<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx15] GPRV4F32:%vreg10 GPRI32:%vreg19
288L		%vreg20<def> = LOADCONST_i32 16; GPRI32:%vreg20
304L		%vreg21<def> = BINARY_OR_i32 %vreg18<kill>, %vreg20<kill>; GPRI32:%vreg21,%vreg18,%vreg20
320L		%vreg22<def> = CUSTOM_ADD_i32 %vreg4<kill>, %vreg21<kill>; GPRI32:%vreg22,%vreg4,%vreg21
336L		GLOBALSTORE_v4f32 %vreg10<kill>, %vreg22<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx25] GPRV4F32:%vreg10 GPRI32:%vreg22
352L		RETURN

# End machine code for function __OpenCL_calPriceVega_kernel.

********** COMPUTING LIVE DEBUG VARIABLES: __OpenCL_calPriceVega_kernel **********
********** DEBUG VARIABLES **********
********** SIMPLE REGISTER COALESCING **********
********** Function: __OpenCL_calPriceVega_kernel
********** JOINING INTERVALS ***********
entry:
16L	%vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
	Considering merging %vreg4 with physreg %Rx1000
	May tie down a physical register, abort!
32L	%vreg2<def> = COPY %Rz1<kill>; GPRI32:%vreg2
	Considering merging %vreg2 with physreg %Rz1
	Register is an unallocatable physreg.
16L	%vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
	Considering merging %vreg4 with physreg %Rx1000
	May tie down a physical register, abort!
********** INTERVALS POST JOINING **********
%vreg7 = [64d,80d:0)  0@64d
%vreg14 = [176d,208d:0)  0@176d
%vreg21 = [304d,320d:0)  0@304d
%vreg2 = [32d,176d:0)  0@32d
%vreg9 = [96d,112d:0)  0@96d
%Rx1000,1.#INF00e+00 = [0L,16d:0)  0@0L-phidef
%vreg16 = [208d,240d:0)  0@208d
%vreg4 = [16d,320d:0)  0@16d
%vreg11 = [128d,192d:0)  0@128d
%vreg18 = [240d,304d:0)  0@240d
%vreg6 = [48d,112d:0)  0@48d
%vreg13 = [160d,176d:0)  0@160d
%vreg20 = [288d,304d:0)  0@288d
%vreg8 = [80d,96d:0)  0@80d
%vreg15 = [192d,208d:0)  0@192d
%vreg22 = [320d,336d:0)  0@320d
%vreg10 = [112d,336d:0)  0@112d
%vreg17 = [224d,240d:0)  0@224d
%Rz1,1.#INF00e+00 = [0L,32d:0)  0@0L-phidef
%vreg12 = [144d,160d:0)  0@144d
%vreg19 = [256d,272d:0)  0@256d
********** INTERVALS **********
%vreg7 = [64d,80d:0)  0@64d
%vreg14 = [176d,208d:0)  0@176d
%vreg21 = [304d,320d:0)  0@304d
%vreg2 = [32d,176d:0)  0@32d
%vreg9 = [96d,112d:0)  0@96d
%Rx1000,1.#INF00e+00 = [0L,16d:0)  0@0L-phidef
%vreg16 = [208d,240d:0)  0@208d
%vreg4 = [16d,320d:0)  0@16d
%vreg11 = [128d,192d:0)  0@128d
%vreg18 = [240d,304d:0)  0@240d
%vreg6 = [48d,112d:0)  0@48d
%vreg13 = [160d,176d:0)  0@160d
%vreg20 = [288d,304d:0)  0@288d
%vreg8 = [80d,96d:0)  0@80d
%vreg15 = [192d,208d:0)  0@192d
%vreg22 = [320d,336d:0)  0@320d
%vreg10 = [112d,336d:0)  0@112d
%vreg17 = [224d,240d:0)  0@224d
%Rz1,1.#INF00e+00 = [0L,32d:0)  0@0L-phidef
%vreg12 = [144d,160d:0)  0@144d
%vreg19 = [256d,272d:0)  0@256d
********** MACHINEINSTRS **********
# Machine code for function __OpenCL_calPriceVega_kernel:
Function Live Ins: %Rz1 in reg%2147483650, %Rx1000 in reg%2147483652

0L	BB#0: derived from LLVM BB %entry
	    Live Ins: %Rz1 %Rx1000
16L		%vreg4<def> = COPY %Rx1000<kill>; GPRI32:%vreg4
32L		%vreg2<def> = COPY %Rz1<kill>; GPRI32:%vreg2
48L		%vreg6<def> = LOADCONST_f32 0.000000e+00; GPRF32:%vreg6
64L		%vreg7<def> = VCREATE_v4f32 %vreg6; GPRV4F32:%vreg7 GPRF32:%vreg6
80L		%vreg8<def> = VINSERT_v4f32 %vreg7<kill>, %vreg6, 197121, 16777216; GPRV4F32:%vreg8,%vreg7 GPRF32:%vreg6
96L		%vreg9<def> = VINSERT_v4f32 %vreg8<kill>, %vreg6, 67109377, 65536; GPRV4F32:%vreg9,%vreg8 GPRF32:%vreg6
112L		%vreg10<def> = VINSERT_v4f32 %vreg9<kill>, %vreg6<kill>, 67305473, 256; GPRV4F32:%vreg10,%vreg9 GPRF32:%vreg6
128L		%vreg11<def> = GET_GLOBAL_ID; GPRV4I32:%vreg11
144L		%vreg12<def> = GET_GLOBAL_ID; GPRV4I32:%vreg12
160L		%vreg13<def> = VEXTRACT_v4i32 %vreg12<kill>, 2; GPRI32:%vreg13 GPRV4I32:%vreg12
176L		%vreg14<def> = SMUL_i32 %vreg13<kill>, %vreg2<kill>; GPRI32:%vreg14,%vreg13,%vreg2
192L		%vreg15<def> = VEXTRACT_v4i32 %vreg11<kill>, 1; GPRI32:%vreg15 GPRV4I32:%vreg11
208L		%vreg16<def> = CUSTOM_ADD_i32 %vreg14<kill>, %vreg15<kill>; GPRI32:%vreg16,%vreg14,%vreg15
224L		%vreg17<def> = LOADCONST_i32 5; GPRI32:%vreg17
240L		%vreg18<def> = SHL_i32 %vreg16<kill>, %vreg17<kill>; GPRI32:%vreg18,%vreg16,%vreg17
256L		%vreg19<def> = CUSTOM_ADD_i32 %vreg4, %vreg18; GPRI32:%vreg19,%vreg4,%vreg18
272L		GLOBALSTORE_v4f32 %vreg10, %vreg19<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx15] GPRV4F32:%vreg10 GPRI32:%vreg19
288L		%vreg20<def> = LOADCONST_i32 16; GPRI32:%vreg20
304L		%vreg21<def> = BINARY_OR_i32 %vreg18<kill>, %vreg20<kill>; GPRI32:%vreg21,%vreg18,%vreg20
320L		%vreg22<def> = CUSTOM_ADD_i32 %vreg4<kill>, %vreg21<kill>; GPRI32:%vreg22,%vreg4,%vreg21
336L		GLOBALSTORE_v4f32 %vreg10<kill>, %vreg22<kill>, 0; flags: FrameSetup mem:ST16[%arrayidx25] GPRV4F32:%vreg10 GPRI32:%vreg22
352L		RETURN

# End machine code for function __OpenCL_calPriceVega_kernel.

********** DEBUG VARIABLES **********
********** Compute Spill Weights **********
********** Function: __OpenCL_calPriceVega_kernel
********** LINEAR SCAN **********
********** Function: __OpenCL_calPriceVega_kernel
fixed intervals:
	%physreg35,1.#INF00e+00 = [0L,16d:0)  0@0L-phidef -> Rx1000
	%physreg76,1.#INF00e+00 = [0L,32d:0)  0@0L-phidef -> Rz1

*** CURRENT ***: %vreg4,4.303977e-03 = [16d,320d:0)  0@16d
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRI32: (preferred: Rx1000) Rx1000
active intervals:
	%vreg4,4.303977e-03 = [16d,320d:0)  0@16d -> Rx1000
inactive intervals:

*** CURRENT ***: %vreg2,3.676471e-03 = [32d,176d:0)  0@32d
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRI32: Ry1000
active intervals:
	%vreg4,4.303977e-03 = [16d,320d:0)  0@16d -> Rx1000
	%vreg2,3.676471e-03 = [32d,176d:0)  0@32d -> Ry1000
inactive intervals:

*** CURRENT ***: %vreg6,1.077586e-02 = [48d,112d:0)  0@48d
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRF32: Rz1000
active intervals:
	%vreg4,4.303977e-03 = [16d,320d:0)  0@16d -> Rx1000
	%vreg2,3.676471e-03 = [32d,176d:0)  0@32d -> Ry1000
	%vreg6,1.077586e-02 = [48d,112d:0)  0@48d -> Rz1000
inactive intervals:

*** CURRENT ***: %vreg7,1.#INF00e+00 = [64d,80d:0)  0@64d
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRV4F32: no free registers
	assigning stack slot at interval %vreg7,1.#INF00e+00 = [64d,80d:0)  0@64d:
		register(s) with min weight(s): R1000 (1.875631e-02)
	Considering 1 candidates: R1000 
			spilling(a): %vreg6,1.077586e-02 = [48d,112d:0)  0@48d
				adding intervals for spills for interval: %vreg6,1.077586e-02 = [48d,112d:0)  0@48d
 +[48d,48S:0)				Added new interval: %vreg23 = [48d,48S:0)  0@invalid
 +[64L,64d:0)				Added new interval: %vreg24 = [64L,64d:0)  0@invalid
 +[80L,80d:0)				Added new interval: %vreg25 = [80L,80d:0)  0@invalid
 +[96L,96d:0)				Added new interval: %vreg26 = [96L,96d:0)  0@invalid
 +[112L,112d:0)				Added new interval: %vreg27 = [112L,112d:0)  0@invalid
			spilling(a): %vreg2,3.676471e-03 = [32d,176d:0)  0@32d
				adding intervals for spills for interval: %vreg2,3.676471e-03 = [32d,176d:0)  0@32d
 +[176L,176d:0)				Added new interval: %vreg29 = [176L,176d:0)  0@invalid
			spilling(a): %vreg4,4.303977e-03 = [16d,320d:0)  0@16d
				adding intervals for spills for interval: %vreg4,4.303977e-03 = [16d,320d:0)  0@16d
 +[256L,256d:0)				Added new interval: %vreg31 = [256L,256d:0)  0@invalid
 +[320L,320d:0)				Added new interval: %vreg32 = [320L,320d:0)  0@invalid
		rolling back to: 16d
			undo changes for: %vreg6,1.077586e-02 = [48d,112d:0)  0@48d
			undo changes for: %vreg2,3.676471e-03 = [32d,176d:0)  0@32d
			undo changes for: %vreg4,4.303977e-03 = [16d,320d:0)  0@16d
active intervals:
inactive intervals:

*** CURRENT ***: %vreg23,1.#INF00e+00 = [48d,48S:0)  0@invalid
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRF32: Rx1000
active intervals:
	%vreg23,1.#INF00e+00 = [48d,48S:0)  0@invalid -> Rx1000
inactive intervals:

*** CURRENT ***: %vreg24,1.#INF00e+00 = [64L,64d:0)  0@invalid
	processing active intervals:
		interval %vreg23,1.#INF00e+00 = [48d,48S:0)  0@invalid expired
	processing inactive intervals:
	allocating current interval from GPRF32: (preferred: Rx1000) Rx1000
active intervals:
	%vreg24,1.#INF00e+00 = [64L,64d:0)  0@invalid -> Rx1000
inactive intervals:

*** CURRENT ***: %vreg7,1.#INF00e+00 = [64d,80d:0)  0@64d
	processing active intervals:
		interval %vreg24,1.#INF00e+00 = [64L,64d:0)  0@invalid expired
	processing inactive intervals:
	allocating current interval from GPRV4F32: R1000
active intervals:
	%vreg7,1.#INF00e+00 = [64d,80d:0)  0@64d -> R1000
inactive intervals:

*** CURRENT ***: %vreg25,1.#INF00e+00 = [80L,80d:0)  0@invalid
	processing active intervals:
	processing inactive intervals:
	allocating current interval from GPRF32: (preferred: Rx1000) no free registers
	assigning stack slot at interval %vreg25,1.#INF00e+00 = [80L,80d:0)  0@invalid:
spillPhysRegAroundRegDefsUses Rx1000 represented by Rx1000
Trying to spill: Rx1000
Assertion failed: false && "Ran out of registers during register allocation!", file ..\..\..\RegAllocLinearScan.cpp, line 1204