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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple style='word-wrap: break-word;-webkit-nbsp-mode: space;-webkit-line-break: after-white-space'><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jakob Stoklund Olesen [mailto:stoklund@2pi.dk] <br><b>Sent:</b> Friday, July 01, 2011 2:56 PM<br><b>To:</b> Villmow, Micah<br><b>Cc:</b> llvmdev@cs.uiuc.edu<br><b>Subject:</b> Re: [LLVMdev] (no subject)<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Jul 1, 2011, at 12:16 PM, Villmow, Micah wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>I'm trying to debug a problem with our custom backend with using a tiered register allocation setup.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Just a little background. My target uses vec4 32bit registers and I want to have three levels of registers setup.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Each vec4 register can have two sub-regs of size vec2 32bit, and each sub-reg, has its own two sub-regs of 32bit each.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>So it looks like this, xyzw -> {xy, zw} -> {x, y, z, w}.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Now the problem I am having is that for some reason, the linearscan allocator is running out of registers to allocate.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>This makes no sense to me as I have 1024 vec4 registers(so 2048 vec2 and 4096 scalars).<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>So I limited to a very small test case where I have 1 vec4(2 vec2 and 4 scalar) registers with<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>a function that requires 1 vec4 register and 5 scalar registers. So, basically what happens<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>is that everything works fine until the live-in register(which is scalar) to the function<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>conflicts with a register that is allocated for the vector(as it is a sub-sub-reg). The<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>linear scan allocator attempts to spill the live-in onto itself and then asserts with<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Courier New"'>assert(<span style='color:blue'>false</span><span class=apple-converted-space> </span>&&<span class=apple-converted-space> </span><span style='color:#A31515'>"Ran out of registers during register allocation!"</span>);.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Courier New"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>I've attached the output of running LLC on my test case, which<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>I don't know if it will be helpful or not, to see what the live<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>interval and reg allocator are doing.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>I'm having trouble debugging this, any idea on where I might want to look?<o:p></o:p></span></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>It's hard to tell without knowing your target. Why does the allocator think there are no free registers in your register class?<o:p></o:p></p><p class=MsoNormal><b><i><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>[Villmow, Micah] That is what I can't figure out. I am only setting the live-in's and some special registers as reserved, and with 1k vector registers, I should not be having any trouble. Somehow the register allocator thinks all registers are used, but if that is the case, it should spill to memory, and even that is failing! If I don't use sub-registers, then I don't have this<o:p></o:p></span></i></b></p><p class=MsoNormal><b><i><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>problem, but then I really can't specify that one register class is a subclass of another.</span></i></b><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p></o:p></span></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><p class=MsoNormal><span class=apple-style-span><span style='font-size:11.5pt;font-family:"Calibri","sans-serif"'>Another question is how do I influence the spill costs? I want to make live in's</span></span><span class=apple-style-span><span style='font-size:13.5pt;font-family:"Menlo","serif"'><o:p></o:p></span></span></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>infinitely expensive to spill, so any superreg or super-super-reg of the live in<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>never gets allocated.<o:p></o:p></span></p></div></div></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div></div><p class=MsoNormal>It's not clear what you mean here. Spill costs are assigned to virtual registers, and virtual registers don't have sub- or super-registers.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>If you mean linear scan's emergency spilling of physical registers, that should never happen anyway. Something else is wrong.<o:p></o:p></p><p class=MsoNormal><b><i><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>[Villmow, Micah] Yeah, i'm hitting this assert to because I'm emergency spilling twice some times. </span></i></b><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p></o:p></span></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>BTW, the new greedy register allocator is way better. It never makes mistakes!<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>/jakob<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div></div></div></body></html>