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陳韋任 wrote:
<blockquote cite="mid:20110517061232.GA174@cs.nctu.edu.tw" type="cite">
<blockquote type="cite">
<pre wrap="">Though, I have to agree with Dan on assessing whether the selection logic is
needed. Do you have an example where the PTX back-end cannot generate code
for some piece of LLVM IR because of the lack of 'not' selection?
</pre>
</blockquote>
<pre wrap=""><!---->
Honestly, I don't have such example yet. Just want to try to implement
some instructions by myself. :p
Regards,
chenwj
</pre>
</blockquote>
Great. I've just been looking through the backend and I believe we can
now handle all the standard IR instructions. For many of them though
it's really just the very simplest implementation, so there's still
loads more to do in handling all the modifiers and various options for
each instruction. That might be a good starting point if you still wish
to contribute, here's a quick ideas list (Justin, Che-Liang, feel free
to comment on any of this):<br>
<br>
* .address_size - New addition to ptx 2.3, which I saw you added as a
target in the backend, so it would be good to explicitly add this
option (much like .target and .version).<br>
<br>
* ftz - We need a new attribute (-mattr=ftz) that matches the nvcc flag
which switches on ftz for all supporting fp operations (add.ftz.f32,
etc)<br>
<br>
* rcp - We could also start matching more complex patterns to support a
larger subset of ptx instructions, I'd use 'mad' as a guide and try and
match 1.0f / value -> rcp(value) to handle reciprocals.<br>
<br>
There are loads more opportunities along these lines, these are just a
few examples that might be a relatively easy starting point for you or
anyone else that's keen on helping out. Beyond this, I'd look at the
PTX spec and nvcc flags for more ideas. :)<br>
<br>
Dan<br>
<br>
<br>
<br>
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