<html><head><base href="x-msg://1963/"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div>On Apr 6, 2011, at 3:31 AM, Rotem, Nadav wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><div lang="EN-US" link="blue" vlink="purple"><div class="WordSection1" style="page: WordSection1; "><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">Hi,<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">I am working on fixing a bug in the x86 codegen and I need help in adding a new type of scheduling constraints.<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">The bug I am fixing is related to SSE instruction scheduling. SSE instructions use the “mxcsr” register for selecting the desired rounding mode. This control register is set/read by an intrinsic. Currently, this intrinsic has no scheduling deps and SSE instructions are scheduled freely before and after calls to this register. When working on this I noticed a case where an SSE instruction (after the intrinsic) was merged with a load instruction (before the intrinsic) during the isel phase. The merged SSE instruction was placed before the call to the intrinsic, producing an incorrect code.<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">In order to establish scheduling constraints, I declared a new phys register and wrapped the control intrinsic and SSE instructions with “Uses/Defs” definitions. My modifications did not add ‘blue edges’ to the scheduling graph. I also tried to change the intrinsic into a memory barrier, but it did not solve this case for obvious reasons.<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">My question is, how do I add these new scheduling constraints ?<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">Thanks,<o:p></o:p></div><div style="margin-top: 0in; margin-right: 0in; margin-bottom: 0.0001pt; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; ">Nadav<o:p></o:p></div></div></div></span></blockquote></div><br><div>Hi Nadav,</div><div><br></div><div>I haven't looked at SSE code, but it sounds like SD nodes for SSE instructions should have a chain operand to their control register write. The scheduler should have no problem with that.</div><div><br></div><div>The problem of isel merging load+SSE is independent of the scheduler of course. That match rule need to somehow respect or preserve the chain operand from SSE to control register.</div><div><br></div><div>-Andy</div></body></html>