<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv=Content-Type content="text/html; charset=us-ascii"><meta name=Generator content="Microsoft Word 12 (filtered medium)"><style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri","sans-serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-compose;
font-family:"Calibri","sans-serif";
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>We are syncing to 2.9 and we are hitting an with our backend in VerifySDNode in SelectionDAG.cpp.<o:p></o:p></p><p class=MsoNormal>The first assert here is failing<o:p></o:p></p><p class=MsoNormal> assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Now, this is new to 2.9 and I am trying to understand what is invalid about what I am generating.<o:p></o:p></p><p class=MsoNormal>What I generate has worked fine from LLVM version 2.4 until now without causing any issues.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This is occuring while I am attempting to lower a vector extract elt to a custom SDNode that my backend understands.<o:p></o:p></p><p class=MsoNormal>I am creating the instruction like as follows:<o:p></o:p></p><p class=MsoNormal>Op = DAG.getNode(AMDILISD::VEXTRACT,<o:p></o:p></p><p class=MsoNormal> Op.getDebugLoc(), Op.getValueType(),<o:p></o:p></p><p class=MsoNormal> Op.getOperand(0),<o:p></o:p></p><p class=MsoNormal> DAG.getTargetConstant(dyn_cast<ConstantSDNode>(Op.getOperand(1)->getZExtValue() + 1), MVT::i32));<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The custom backend instruction is defined as follows:<o:p></o:p></p><p class=MsoNormal>def SDTIL_GenVecExtract : SDTypeProfile<1, 2, [<o:p></o:p></p><p class=MsoNormal> SDTCisEltOfVec<0, 1>, SDTCisVT<2, i32><o:p></o:p></p><p class=MsoNormal> ]>;<o:p></o:p></p><p class=MsoNormal>def IL_vextract : SDNode<"AMDILISD::VEXTRACT", SDTIL_GenVecExtract>;<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>defm VEXTRACT : VectorExtract<IL_vextract>;<o:p></o:p></p><p class=MsoNormal>// Class that handles the various vector extract patterns<o:p></o:p></p><p class=MsoNormal>multiclass VectorExtract<SDNode OpNode> {<o:p></o:p></p><p class=MsoNormal>...<o:p></o:p></p><p class=MsoNormal>def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>;<o:p></o:p></p><p class=MsoNormal>...<o:p></o:p></p><p class=MsoNormal>}<o:p></o:p></p><p class=MsoNormal>class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode><o:p></o:p></p><p class=MsoNormal>: ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),<o:p></o:p></p><p class=MsoNormal> "mov $dst, $src0",<o:p></o:p></p><p class=MsoNormal> [(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;<o:p></o:p></p><p class=MsoNormal>class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern><o:p></o:p></p><p class=MsoNormal>: Instruction {<o:p></o:p></p><p class=MsoNormal> let Namespace = "AMDIL";<o:p></o:p></p><p class=MsoNormal> dag OutOperandList = outs;<o:p></o:p></p><p class=MsoNormal> dag InOperandList = ins;<o:p></o:p></p><p class=MsoNormal> ILOpCode operation = op;<o:p></o:p></p><p class=MsoNormal> let Pattern = pattern;<o:p></o:p></p><p class=MsoNormal> let AsmString = !strconcat(asmstr, "\n");<o:p></o:p></p><p class=MsoNormal> bit hasIEEEFlag = 0;<o:p></o:p></p><p class=MsoNormal> bit hasZeroOpFlag = 0;<o:p></o:p></p><p class=MsoNormal>}<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I cannot see how I am doing anything wrong here. I've looked at the equivalent x86 shuffle<o:p></o:p></p><p class=MsoNormal> instructions and they don't look that much different. The big difference is they do not<o:p></o:p></p><p class=MsoNormal>specify the SDTCisEltOfVec constraint.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Any ideas?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<o:p></o:p></p><p class=MsoNormal>Micah<o:p></o:p></p></div></body></html>