<html><head><base href="x-msg://317/"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Feb 6, 2011, at 11:32 PM, Jonas Paulsson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><div class="hmmessage" style="font-size: 10pt; font-family: Tahoma; ">When I compile the following program (for ARM):<br><br> for(i=0;i<n2;i+=n3)<br> {<br> s+=a[i];<br> }<br><br>, with GCC, I get the following loop body, with a post-modify load:<br><br>.L4:<br> add r1, r1, r3<br> ldr r4, [ip], r6<br> rsb r5, r3, r1<br> cmp r2, r5<br> add r0, r0, r4<br> bgt .L4<br><br>With LLVM, however, I get:<br><br>.LBB0_3: @ %for.body<br> @ =>This Inner Loop Header: Depth=1<br> add r12, lr, r3<br> ldr lr, [r0, lr, lsl #2]<br> add r1, lr, r1<br> cmp r12, r2<br> mov lr, r12<br> blt .LBB0_3<br><br>, which does not seem to be auto-incrementing, I think.<br></div></span></blockquote><div><br></div>No, it's not using a post-increment load. There are two separate requirements to make this happen:</div><div><br></div><div>* LSR (the loop strength reduce pass) needs to transform the loop so that the load address is a simple induction variable.</div><div><br></div><div>* The instruction selection needs to recognize the opportunity for folding the address increment into the load.</div><div><br></div><div>In this case, LSR is not doing the right thing.</div><div><br><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><div class="hmmessage" style="font-size: 10pt; font-family: Tahoma; "><br>I wonder what I should do to get loops auto-incing generally, for instance in this simple loop:<br><br> for(i=0;i<256;i++)<br> {<br> s+=a[i];<br> }<br><br>, which now yields<br><br>.LBB0_1: @ %for.body<br> @ =>This Inner Loop Header: Depth=1<br> ldr r3, [r0, r2]<br> add r2, r2, #4<br> add r1, r3, r1<br> cmp r2, #1, 22 @ 1024<br> bne .LBB0_1<br><br>, which uses r0 as base address with r2 as offset. On my target, it is much preferred to use auto-inc in cases like this. I repeat my question, as I don't quite understand why the ldr/add is used by ARM here, instead of post-inc. I guess I would like the DAG combiner to work in cases like this, but it does not seem to do so.</div></span></blockquote><br></div><div>Same issue. The DAG combiner can't handle it because LSR didn't expose the load address as a simple induction variable. E.G., if the code was something like:</div><div><br></div><div> ldr r3, [r2]</div><div> add r2, r2, #4</div><div><br></div><div>...then the DAG combiner could do something with it.</div><div><br></div><div>Feel free to file a bug report on these issues.</div></body></html>