Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. <div><br></div><div>For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during register allocation, or how can I tell from (1) that I cannot execute %reg16385<def> = COPY %reg16390. Furthermore, how should I handle this case.</div>
<div><br></div><div>1:</div><div><div># Machine code for function test5:</div><div>Frame Objects:</div><div> fi#-2: size=2, align=4, fixed, at location [SP+8]</div><div> fi#-1: size=2, align=8, fixed, at location [SP+4]</div>
<div>Function Live Outs: %AX</div><div><br></div><div>BB#0: derived from LLVM BB %entry</div><div> %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390</div><div>
%reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390</div><div> %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391</div>
<div> %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391</div><div> Successors according to CFG: BB#1</div><div>... </div></div><div><br></div><div>2: </div><div>BB#0: derived from LLVM BB %entry</div>
<div> %EDX<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2]</div><div> %CX<def> = COPY %EDX</div><div> %ESI<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1]</div>
<div> %AX<def> = COPY %ESI</div><div><br></div><div><br></div><div><br></div><div><br></div><div>Below is the full code for the function.</div><div><br></div><div><div># Machine code for function test5:</div>
<div>Frame Objects:</div><div> fi#-2: size=2, align=4, fixed, at location [SP+8]</div><div> fi#-1: size=2, align=8, fixed, at location [SP+4]</div><div>Function Live Outs: %AX</div><div><br></div><div>BB#0: derived from LLVM BB %entry</div>
<div> %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390</div><div> %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390</div>
<div> %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391</div><div> %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391</div>
<div> Successors according to CFG: BB#1</div><div><br></div><div>BB#1: derived from LLVM BB %bb</div><div> Predecessors according to CFG: BB#0 BB#1</div><div> %reg16386<def> = PHI %reg16385, <BB#0>, %reg16394, <BB#1>; GR16:%reg16386,16385,16394</div>
<div> %reg16387<def> = PHI %reg16384, <BB#0>, %reg16398, <BB#1>; GR16:%reg16387,16384,16398</div><div> %reg16393<def> = MOV16ri 1; GR16:%reg16393</div><div> %reg16398<def> = COPY %reg16387; GR16:%reg16398,16387</div>
<div> %reg16398<def> = XOR16rr %reg16398, %reg16386, %EFLAGS<imp-def>; GR16:%reg16398,16386</div><div> %reg16397<def> = COPY %reg16398; GR16:%reg16397,16398</div><div> %reg16397<def> = XOR16ri %reg16397, 32767, %EFLAGS<imp-def>; GR16:%reg16397</div>
<div> %reg16396<def> = COPY %reg16397; GR16:%reg16396,16397</div><div> %reg16396<def> = AND16rr %reg16396, %reg16386, %EFLAGS<imp-def>; GR16:%reg16396,16386</div><div> %reg16394<def> = COPY %reg16396; GR16:%reg16394,16396</div>
<div> %reg16394<def> = SHL16ri %reg16394, 1, %EFLAGS<imp-def>; GR16:%reg16394</div><div> CMP16ri %reg16394, 0, %EFLAGS<imp-def>; GR16:%reg16394</div><div> JNE_4 <BB#1>, %EFLAGS<imp-use></div>
<div> Successors according to CFG: BB#2 BB#1</div><div><br></div><div>BB#2: derived from LLVM BB %bb12</div><div> Predecessors according to CFG: BB#1</div><div> %AX<def> = COPY %reg16398; GR16:%reg16398</div>
<div> RET</div><div><br></div><div># End machine code for function test5.</div></div><div><br></div><div><div># After Register Allocation:</div><div># Machine code for function test5:</div><div>Frame Objects:</div>
<div> fi#-2: size=2, align=4, fixed, at location [SP+8]</div><div> fi#-1: size=2, align=8, fixed, at location [SP+4]</div><div>Function Live Outs: %AX</div><div><br></div><div>BB#0: derived from LLVM BB %entry</div><div>
%EDX<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2]</div><div> %CX<def> = COPY %EDX</div><div> %ESI<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1]</div>
<div> %AX<def> = COPY %ESI</div><div> Successors according to CFG: BB#1</div><div><br></div><div>BB#1: derived from LLVM BB %bb</div><div> Predecessors according to CFG: BB#0 BB#1</div><div> %AX<def> = XOR16rr %AX, %CX, %EFLAGS<imp-def></div>
<div> %DX<def> = COPY %AX</div><div> %DX<def> = XOR16ri %DX, 32767, %EFLAGS<imp-def></div><div> %DX<def> = AND16rr %DX, %CX, %EFLAGS<imp-def></div><div> %CX<def> = SHL16ri %CX, 1, %EFLAGS<imp-def></div>
<div> CMP16ri %CX, 0, %EFLAGS<imp-def></div><div> JNE_4 <BB#1>, %EFLAGS<imp-use></div><div> Successors according to CFG: BB#2 BB#1</div><div><br></div><div>BB#2: derived from LLVM BB %bb12</div>
<div> Predecessors according to CFG: BB#1</div><div> RET</div></div><div><br></div><div><br></div>