<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div>Ah! Okay. So it's not the generic code. Yes, it's probably a bug that the memoperands aren't propagated to the new instruction. Please file a bug report with a small testcase.</div><div><br></div>-bw<div><br><div><div>On Sep 7, 2010, at 4:07 PM, Akira Hatanaka wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD instruction.<br> <br> Ops.pop_back();<br> Ops.pop_back();<br><br> // Form the pair instruction.<br> if (isLd) {<br>
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,<br> dl, TII->get(NewOpc))<br> .addReg(EvenReg, RegState::Define)<br> .addReg(OddReg, RegState::Define)<br>
.addReg(BaseReg);<br> if (!isT2)<br> MIB.addReg(OffReg);<br> MIB.addImm(Offset).addImm(Pred).addReg(PredReg);<br> ++NumLDRDFormed;<br><br><br><div class="gmail_quote">
On Tue, Sep 7, 2010 at 1:31 PM, Bill Wendling <span dir="ltr"><<a href="mailto:wendling@apple.com">wendling@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div class="im">On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote:<br>
<br>
> I have two questions regarding MachineMemOperands and dependence information.<br>
><br>
> Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.<br>
><br>
> (before optimization)<br>
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10]<br>
> %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021]<br>
><br>
> (after optimization)<br>
> %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0<br>
><br>
> Are there any reasons they need to be removed?<br>
> Would it break something if both MachineMemOperands were added to the newly generated instruction?<br>
><br>
> (after optimization)<br>
> %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0; mem:LD4[%uglygep10], mem:LD4[%uglygep2021]<br>
<br>
</div>If I had to guess, I would think it's because of how LDR is defined:<br>
<br>
def addrmodepc : Operand<i32>,<br>
ComplexPattern<i32, 2, "SelectAddrModePC", []> {<br>
let PrintMethod = "printAddrModePCOperand";<br>
let MIOperandInfo = (ops GPR, i32imm);<br>
}<br>
def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,<br>
"ldr", "\t$dst, $addr",<br>
[(set GPR:$dst, (load addrmode2:$addr))]>;<br>
<br>
It's using addrmodepc, which is a ComplexPattern. The TableGen code cannot handle resetting the memoperands if it's dealing with a ComplexPattern. There's a similar bug in the X86 target.<br>
<font color="#888888"><br>
-bw<br>
<br>
</font></blockquote></div><br>
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